W9864G6IH
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
CAS
GENERATOR
COMMAND
DECODER
WE
ROW DECODER
COLUMN DECODER
COLUMN DECODER
ROW DECODER
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A0
A9
A11
BS0
BS1
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN
COUNTER
DQ
BUFFER
DQ0
DQ15
REFRESH
COUNTER
UDQM
LDQM
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 256 * 16
-6-
Publication Release Date:Mar. 31, 2008
Revision A05