WM8569
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
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Figure 1 ADC and DAC Master Clock Timing Requirements
Test Conditions
o
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, T
A
= +25 C, fs = 48kHz, DACMCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width
high
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
Table 1 Master Clock Timing Requirements
t
MCLKH
t
MCLKL
t
MCLKY
11
11
28
40:60
60:40
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL AUDIO INTERFACE – MASTER MODE
Figure 2 Audio Interface – Master Mode
w
PP Rev 1.1 December 2005
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