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WM8569
DACBCLK/
ADCBCLK
(Output)
DACLRC/
ADCLRC
(Output)
t
DL
t
DDA
DOUT
DIN
t
DST
t
DHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T
A
= +25
o
C, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
DACLRC/ADCLRC
propagation delay from
DACBCLK/ADCBCLK
falling edge
DOUT propagation delay
from ADCBCLK falling edge
DIN setup time to
DACBCLK rising edge
DIN hold time from
DACBCLK rising edge
SYMBOL
t
DL
TEST CONDITIONS
MIN
0
TYP
MAX
10
UNIT
ns
Audio Data Input Timing Information
t
DDA
t
DST
t
DHT
0
10
10
10
ns
ns
ns
Table 2 Digital Audio Data Timing – Master Mode
w
PP Rev 1.1 December 2005
9