R
Spartan-IIE FPGA Family:
Functional Description
0
Product Specification
As can be seen in
the CLBs form the central logic
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
Values stored in static memory cells control all the config-
urable logic elements and interconnect resources. These
values load into the memory cells on power-up, and can
reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the fol-
lowing sections.
DS077-2 (v2.3) June 18, 2008
Architectural Description
Spartan-IIE FPGA Array
The Spartan
®
-IIE user-programmable gate array, shown in
is composed of five major configurable elements:
•
•
•
•
•
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
DLL
DLL
BLOCK RAM
CLBs
CLBs
BLOCK RAM
CLBs
CLBs
DLL
I/O LOGIC
DS077_01_052102
Figure 3:
Basic Spartan-IIE Family FPGA Block Diagram
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DS077-2 (v2.3) June 18, 2008
Product Specification
BLOCK RAM
DLL
BLOCK RAM
9
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