R
Virtex-II Platform FPGAs: Introduction and Overview
Table 1:
Virtex-II Field-Programmable Gate Array Family Members
CLB
(1 CLB = 4 slices = Max 128 bits)
System
Gates
40K
80K
250K
500K
1M
1.5M
2M
3M
4M
6M
8M
Array
Row x Col.
8x8
16 x 8
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
112 x 104
Maximum
Distributed
RAM Kbits
8
16
48
96
160
240
336
448
720
1,056
1,456
Multiplier
Blocks
4
8
24
32
40
48
56
96
120
144
168
SelectRAM Blocks
18 Kbit
Blocks
4
8
24
32
40
48
56
96
120
144
168
Max RAM
(Kbits)
72
144
432
576
720
864
1,008
1,728
2,160
2,592
3,024
Max I/O
Pads
(1)
88
120
200
264
432
528
624
720
912
1,104
1,108
Device
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Slices
256
512
1,536
3,072
5,120
7,680
10,752
14,336
23,040
33,792
46,592
DCMs
4
4
8
8
8
8
8
12
12
12
12
Notes:
1. See details in
.
General Description
The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire-
less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
the Virtex-II family comprises 11 members, ranging
from 40K to 8M system gates.
Wire-bond packages CS, FG, and BG are optionally avail-
abe in Pb-free versions CSG, FGG, and BGG. See
shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table
at
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.
Table 2:
Maximum Number of User I/O Pads
Device
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Wire-Bond
88
120
200
264
328
392
-
516
-
-
-
Flip-Chip
-
-
-
-
432
528
624
720
912
1,104
1,108
Packaging
Offerings include ball grid array (BGA) packages with
0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-
ditional wire-bond interconnects, flip-chip interconnect is
used in some of the BGA offerings. The use of flip-chip
interconnect offers more I/Os than is possible in wire-bond
versions of the similar packages. Flip-chip construction
offers the combination of high pin count with high thermal
capacity.
DS031-1 (v3.5) November 5, 2007
Product Specification
Module 1 of 4
2
XILINX [ XILINX, INC ]
