R
Spartan-3 1.2V FPGA Family: Functional Description
match the characteristic impedance of the transmission line.
This adjustment process compensates for differences in I/O
impedance that can result from normal variation in the
ambient temperature, the supply voltage and the manufac-
turing process. When the output driver turns off, the series
termination, by definition, approaches a very high imped-
ance; in contrast, parallel termination resistors remain at the
targeted values.
DCI is available only for certain I/O standards, as listed in
Table 6. DCI is selected by applying the appropriate I/O
standard extensions to symbols or components. There are
five basic ways to configure terminations, as shown in
Table 7. The DCI I/O standard determines which of these
terminations is put into effect.
Table 6: DCI I/O Standards
V
CCO (V)
Termination Type
Category of Signal
Standard
For
Outputs
For
Inputs
VREF for
Inputs (V)
Signal Standard
At Output
At Input
Single-Ended
Gunning
Transceiver Logic
GTL_DCI
1.2
1.5
1.5
1.5
1.8
1.8
1.8
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.8
2.5
2.5
1.2
1.5
1.5
1.5
1.8
1.8
1.8
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
1.8
2.5
2.5
0.8
1.0
0.75
0.9
0.9
0.9
1.1
-
Single
Single
GTLP_DCI
High-Speed
Transceiver Logic
HSTL_I_DCI
None
None
None
Split
Split
Single
Split
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
None
Single
None
Low-Voltage CMOS LVDCI_15
LVDCI_18
Controlled impedance
driver
-
LVDCI_25
-
LVDCI_33
-
LVDCI_DV2_15
-
Controlled driver with
half-impedance
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
SSTL18_I_DCI
SSTL2_I_DCI
SSTL2_II_DCI
-
-
-
Stub Series
Terminated Logic
0.9
1.25
1.25
25-Ohm driver
25-Ohm driver
Split
Split with 25-Ohm driver
Differential
Low-Voltage
Differential
Signalling
LVDS_25_DCI
2.5
2.5
2.5
2.5
-
-
None
Split on
each line
of pair
LVDSEXT_25_DCI
Notes:
1. Bank 5 of any Spartan-3 device in a VQ100 or TQ144 package does not support DCI signal standards.
6
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DS099-2 (v1.2) July 11, 2003
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Advance Product Specification
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