R
Spartan-3 1.2V FPGA Family: Functional Description
The DCI feature operates independently for each of the
device’s eight banks. Each bank has an "N" reference pin
(VRN) and a "P" reference pin, (VRP), to calibrate driver
and termination resistance. Only when using a DCI stan-
dard on a given bank do these two pins function as VRN
and VRP. When not using a DCI standard, the two pins func-
tion as user I/Os. As shown in Figure 3, add an external ref-
erence resistor to pull the VRN pin up to VCCO and another
reference resistor to pull the VRP pin down to GND. Both
resistors have the same value — commonly 50 Ohms —
with one-percent tolerance, which is either the characteristic
impedance of the line or twice that, depending on the DCI
standard in use. Standards having a symbol name that con-
tains the letters “DV2” use a reference resistor value that is
twice the line impedance. DCI adjusts the output driver
impedance to match the reference resistors’ value or half
that, according to the standard. DCI always adjusts the
on-chip termination resistors to directly match the reference
resistors’ value.
Spartan-3 devices in these packages support eight inde-
pendent VCCO supplies.
Bank 0
Bank 1
Bank 5
Bank 4
DS099-2_03_060102
Figure 4: Spartan-3 I/O Banks (top view)
In contrast, the 144-pin Thin Quad Flat Pack (TQ144) pack-
age ties VCCO together internally for the pair of banks on
each side of the device. For example, the VCCO Bank 0 and
the VCCO Bank 1 lines are tied together. The interconnected
bank-pairs are 0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3
devices in the TQ144 package support four independent
One of eight
I/O Banks
V
CCO
R
(1%)
(1%)
REF
VRN
VRP
V
CCO supplies.
R
REF
Spartan-3 Compatibility
Within the Spartan-3 family, all devices are pin-compatible
by package. When the need for future logic resources out-
grows the capacity of the Spartan-3 device in current use, a
larger device in the same package can serve as a direct
replacement. Larger devices may add extra VREF and VCCO
lines to support a greater number of I/Os. In the larger
device, more pins can convert from user I/Os to VREF lines.
Also, additional VCCO lines are bonded out to pins that were
“not connected” in the smaller device. Thus, it is important
to plan for future upgrades at the time of the board’s initial
design by laying out connections to the extra pins.
DS099-2_04_091602
Figure 3: Connection of Reference Resistors (RREF
)
The rules guiding the use of DCI standards on banks are as
follows:
1. No more than one DCI I/O standard with a Single
Termination is allowed per bank.
2. No more than one DCI I/O standard with a Split
Termination is allowed per bank.
3. Single Termination, Split Termination, Controlled-
Impedance Driver, and Controlled-Impedance Driver
with Half Impedance can co-exist in the same bank.
The Spartan-3 family is not pin-compatible with any previ-
ous Xilinx FPGA family.
See also The Organization of IOBs into Banks, page 8.
Rules Concerning Banks
When assigning I/Os to banks, it is important to follow the
following VCCO rules:
The Organization of IOBs into Banks
IOBs are allocated among eight banks, so that each side of
the device has two banks, as shown in Figure 4. For all
packages, each bank has independent VREF lines. For
example, VREF Bank 3 lines are separate from the VREF
lines going to all other banks.
1. Leave no VCCO pins unconnected on the FPGA.
2. Set all VCCO lines associated with the (interconnected)
bank to the same voltage level.
3. The VCCO levels used by all standards assigned to the
I/Os of the (interconnected) bank(s) must agree. The
Xilinx development software checks for this. Tables 4, 5,
and 6 describe how different standards use the VCCO
supply.
For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat
Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine
Pitch Ball Grid Array (FG) packages, each bank has dedi-
cated VCCO lines. For example, the VCCO Bank 7 lines are
separate from the VCCO lines going to all other banks. Thus,
8
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DS099-2 (v1.2) July 11, 2003
Advance Product Specification
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