R
Spartan-3 FPGA Family: Introduction and Ordering Information
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before pow-
ering on the FPGA, configuration data is stored externally in
a PROM or some other nonvolatile medium either on or off
the board. After applying power, the configuration data is
written to the FPGA using any of five different modes: Mas-
ter Parallel, Slave Parallel, Master Serial, Slave Serial and
Boundary Scan (JTAG). The Master and Slave Parallel
modes use an 8-bit wide SelectMAP™ port.
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
Standard
Category
Single-Ended
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 17 sin-
gle-ended standards and seven differential standards as
listed in
Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections.
shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
Table 2:
Signal Standards Supported by the Spartan-3 Family
Description
Gunning Transceiver Logic
High-Speed Transceiver Logic
V
CCO
(V)
N/A
1.5
1.8
Class
Terminated
Plus
HSTL
I
III
I
II
III
LVCMOS
Low-Voltage CMOS
1.2
1.5
1.8
2.5
3.3
LVTTL
PCI
SSTL
Low-Voltage Transistor-Transistor Logic
Peripheral Component Interconnect
Stub Series Terminated Logic
3.3
3.0
1.8
2.5
Differential
Symbol
GTL
GTLP
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
PCI33_3
SSTL18_I
SSTL2_I
SSTL2_II
DCI
Option
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
GTL
N/A
N/A
N/A
N/A
N/A
N/A
33 MHz
N/A
I
II
LDT
LVDS
Lightning Data Transport
(HyperTransport™)
Low-Voltage Differential Signaling
2.5
N/A
Standard
Bus
Extended Mode
Ultra
LDT_25
LVDS_25
BLVDS_25
LVDSEXT_25
ULVDS_25
LVPECL_25
RSDS_25
No
Yes
No
Yes
No
No
No
LVPECL
RSDS
Low-Voltage Positive Emitter-Coupled
Logic
Reduced-Swing Differential Signaling
2.5
2.5
N/A
N/A
DS099-1 (v1.2) December 24, 2003
Advance Product Specification
1-800-255-7778
3
XILINX [ XILINX, INC ]
