R
Spartan-3 FPGA Family: Pinout Descriptions
Table 69:
Spartan-3 FPGA Pin Definitions
(Continued)
Pin Name
DONE
Direction
Bidirectional with open-drain
or totem-pole Output
Description
Configuration Done, Delay Start-up Sequence:
A Low-to-High output transition on this bidirectional pin signals the
end of the configuration process.
The FPGA produces a Low-to-High transition on this pin to
indicate that the configuration process is complete. The DriveDone
bitstream generation option defines whether this pin functions as
a totem-pole output that actively drives High or as an open-drain
output. An open-drain output requires a pull-up resistor to produce
a High logic level. The open-drain option permits the DONE lines
of multiple FPGAs to be tied together, so that the common node
transitions High only after all of the FPGAs have completed
configuration. Externally holding the open-drain output Low delays
the start-up sequence, which marks the transition to user mode.
M0, M1, M2
Input
Configuration Mode Selection:
These inputs select the configuration mode. The logic levels
applied to the mode pins are sampled on the rising edge of INIT_B.
See
These pins have an internal pull-up resistor to
VCCAUX during configuration, making Slave Serial the default
configuration mode.
HSWAP_EN
Input
Disable Pull-up Resistors During Configuration:
A Low on this pin enables pull-up resistors on all pins that are not
actively involved in the configuration process. A High value
disables all pull-ups, allowing the non-configuration pins to float.
JTAG:
JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN pin)
TCK
Input
JTAG Test Clock:
The TCK clock signal synchronizes all JTAG port operations. This
pin has an internal pull-up resistor to VCCAUX during
configuration.
TDI
Input
JTAG Test Data Input:
TDI is the serial data input for all JTAG instruction and data
registers. This pin has an internal pull-up resistor to VCCAUX
during configuration.
TMS
Input
JTAG Test Mode Select:
The serial TMS input controls the operation of the JTAG port. This
pin has an internal pull-up resistor to VCCAUX during
configuration.
TDO
Output
JTAG Test Data Output:
TDO is the serial data output for all JTAG instruction and data
registers. This pin has an internal pull-up resistor to VCCAUX
during configuration.
VCCO:
I/O bank output voltage supply pins
VCCO_#
Supply
Power Supply for Output Buffer Drivers (per bank):
These pins power the output drivers within a specific I/O bank.
DS099-4 (v2.4) June 25, 2008
Product Specification
103
XILINX [ XILINX, INC ]
