Spartan-3 FPGA Family: Pinout Descriptions
Table 68:
Types of Pins on Spartan-3 FPGAs
(Continued)
Type/
Color
Code
VREF
R
Description
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF
pins in the same bank, provides a reference voltage input for certain I/O
standards. If used for a reference voltage within a bank, all VREF pins
within the bank must be connected.
Dedicated ground pin. The number of GND pins depends on the package
used. All must be connected.
Dedicated auxiliary power supply pin. The number of VCCAUX pins
depends on the package used. All must be connected to +2.5V.
Dedicated internal core logic power supply pin. The number of VCCINT
pins depends on the package used. All must be connected to +1.2V.
Dedicated I/O bank, output buffer power supply pin. Along with other
VCCO pins in the same bank, this pin supplies power to the output buffers
within the I/O bank and sets the input threshold voltage for some I/O
standards.
Pin Name(s) in Type
IO/VREF_#
IO_Lxxy_#/VREF_#
GND
VCCAUX
VCCINT
VCCO
GND
VCCAUX
VCCINT
VCCO_#
CP132 and TQ144 Packages
Only:
VCCO_LEFT, VCCO_TOP,
VCCO_RIGHT,
VCCO_BOTTOM
IO_Lxxy_#/GCLK0,
IO_Lxxy_#/GCLK1,
IO_Lxxy_#/GCLK2,
IO_Lxxy_#/GCLK3,
IO_Lxxy_#/GCLK4,
IO_Lxxy_#/GCLK5,
IO_Lxxy_#/GCLK6,
IO_Lxxy_#/GCLK7
N.C.
GCLK
Dual-purpose pin that is either a user-I/O pin or an input to a specific global
buffer input. Every package has eight dedicated GCLK pins.
N.C.
This package pin is not connected in this specific device/package
combination but may be connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 7.
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indi-
cates differential output capability. The “xx” field is a
two-digit integer, unique to each bank that identifies a differ-
ential pin-pair. The ‘y’ field is either ‘P’ for the true signal or
‘N’ for the inverted signal in the differential pair. The ‘#’ field
is the I/O bank number.
Pin Definitions
provides a brief description of each pin listed in the
Spartan-3 FPGA pinout tables and package footprint dia-
grams. Pins are categorized by their pin type, as listed in
See
for
more information.
100
Product Specification
XILINX [ XILINX, INC ]
