R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 66:
Timing for the Master and Slave Parallel Configuration Modes
(Continued)
Symbol
Hold Times
Description
The time from the rising transition at the CCLK pin to the point
when data is last held at the D0-D7 pins
The time from the rising transition at the CCLK pin to the point
when a logic level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point
when a logic level is last held at the RDWR_B pin
CCLK input pin High pulse width
CCLK input pin Low pulse width
Frequency of the
clock signal at the
CCLK input pin
No bitstream
compression
Not using the BUSY pin
(3)
Using the BUSY pin
Slave/
Master
Both
All Speed Grades
Min
0
0
0
Max
-
-
-
Units
ns
ns
ns
T
SMCCD
T
SMCCCS
T
SMWCC(2)
Clock Timing
T
CCH
T
CCL
F
CCPAR
Slave
5
5
0
0
0
0
∞
∞
50
66
20
50
+50%
ns
ns
MHz
MHz
MHz
MHz
-
With bitstream compression
During STARTUP phase
Master
ΔF
CCPAR
Variation from the CCLK output frequency set using the BitGen
option ConfigRate
–50%
Notes:
1. The numbers in this table are based on the operating conditions set forth in
2. RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the
driver impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B
High when CS_B is Low.
3. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
4. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
DS099-3 (v2.4) June 25, 2008
Product Specification
95
XILINX [ XILINX, INC ]
