R
Spartan-3 FPGA Family: DC and Switching Characteristics
Revision History
Date
04/11/03
07/11/03
02/06/04
Version No.
1.0
1.1
1.2
Initial Xilinx release.
Description
Extended Absolute Maximum Rating for junction temperature in
Added numbers for typical quiescent
supply current (Table
and DLL timing.
Revised V
IN
maximum rating (Table
Added power-on requirements (Table
leakage current number
and differential output voltage levels (Table
for Rev. 0. Published new quiescent current numbers
Updated pull-up and pull-down resistor strengths (Table
Added LVDCI_DV2 and LVPECL
standards (Table
and
Changed CCLK setup time (Table
and
Added timing numbers from v1.29 speed files as well as DCM timing (Table
through
Added reference to errata documents on
Clarified Absolute Maximum Ratings and added ESD
information (Table
Explained V
CCO
ramp time measurement (Table
Clarified I
L
specification
Updated quiescent current numbers and added information on power-on and surplus current
Adjusted V
REF
range for HSTL_III and HSTL_I_18 and changed V
IH
min for LVCMOS12 (Table
Added note limiting V
TT
range for SSTL2_II signal standards (Table
Calculated V
OH
and V
OL
levels for
differential standards (Table
Updated Switching Characteristics with speed file v1.32 (Table
through
and
through
Corrected IOB test conditions (Table
Updated DCM timing with
latest characterization data (Table
through
Improved DCM CLKIN pulse width specification
Recommended use of Virtex-II FPGA Jitter calculator (Table
Improved DCM PSCLK pulse
width specification (Table
Changed Phase Shifter lock time parameter (Table
Because the BitGen
option Centered_x#_y# is not necessary for Variable Phase Shift mode, removed BitGen command table and
referring text. Adjusted maximum CCLK frequency for the slave serial and parallel configuration modes
Inverted CCLK waveform (Figure
Adjusted JTAG setup times (Table
Updated timing parameters to match v1.35 speed file. Improved V
CCO
ramp time specification (Table
Added a note limiting the rate of change of V
CCAUX
Added typical quiescent current values for the
XC3S2000, XC3S4000, and XC3S5000 (Table
Increased I
OH
and I
OL
for SSTL2-I and SSTL2-II standards
Added SSO guidelines for the VQ, TQ, and PQ packages as well as edited SSO guidelines for the
FT and FG packages (Table
Added maximum CCLK frequencies for configuration using compressed
bitstreams (Table
and
Added specifications for the HSLVDCI standards (Table
and
Updated timing parameters to match v1.37 speed file. All Spartan-3 part types, except XC3S5000, promoted
to Production status. Removed V
CCO
ramp rate restriction from all mask revision ‘E’ and later devices
Added equivalent resistance values for internal pull-up and pull-down resistors (Table
Added
worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000 (Table
Added industrial
temperature range specification and improved typical quiescent current values (Table
Improved the DLL
minimum clock input frequency specification from 24 MHz down to 18 MHz (Table
Improved the DFS
minimum and maximum clock output frequency specifications (Table
Added new miscellaneous
DCM specifications (Table
primarily affecting Industrial temperature range applications. Updated
and
for QFP packages. Added information on
SSTL18_II I/O standard and timing to support DDR2 SDRAM interfaces. Added differential (or complementary
single-ended) DIFF_HSTL_II_18 and DIFF_SSTL2_II I/O standards, including DCI terminated versions. Added
electro-static discharge (ESD) data for the XC3S2000 and larger FPGAs (Table
Added link to Spartan-3
errata notices and how to receive automatic notifications of data sheet or errata changes.
03/04/04
08/24/04
1.3
1.4
12/17/04
1.5
08/19/05
1.6
04/03/06
2.0
Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in
Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic
and I/O paths. Corrected labels for R
PU
and R
PD
and updated R
PD
conditions for in
Added final
mask revision ‘E’ specifications for LVDS_25, RSDS_25, LVDSEXT_25 differential outputs to
Added BLVDS termination requirements to
Improved recommended Simultaneous Switching
Outputs (SSOs) limits in
for quad-flat packaged based on silicon testing using devices soldered
on a printed circuit board. Updated Note 2 in
Updated Note 6 in
Added INIT_B
minimum pulse width specification, T
INIT
, to
Updated document links.
04/26/06
2.1
DS099-3 (v2.4) June 25, 2008
Product Specification
97
XILINX [ XILINX, INC ]
