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Spartan-3 FPGA Family:
Introduction and Ordering
Information
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DS099-1 (v2.4) June 25, 2008
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Product Specification
Introduction
The Spartan
®
-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from the Virtex
®
-II platform technol-
ogy. These Spartan-3 FPGA enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
The Spartan-3 FPGAs are the first platform among several
within the
Features
•
Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
-
Densities up to 74,880 logic cells
SelectIO™ interface signaling
-
Up to 633 I/O pins
-
622 Mb/s data transfer rate per I/O
-
18 single-ended signal standards
-
8 differential I/O standards including LVDS, RSDS
-
Termination by Digitally Controlled Impedance
-
Signal swing ranging from 1.14V to 3.465V
-
Double Data Rate (DDR) support
-
up to 333 Mbps
Logic resources
-
Abundant logic cells with shift register capability
-
Wide, fast multiplexers
-
Fast look-ahead carry logic
-
Dedicated 18 x 18 multipliers
-
JTAG logic compatible with IEEE 1149.1/1532
SelectRAM™ hierarchical memory
-
Up to 1,872 Kbits of total block RAM
-
Up to 520 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
-
Clock skew elimination
-
Frequency synthesis
-
High resolution phase shifting
Eight global clock lines and abundant routing
•
•
•
•
•
•
•
•
Fully supported by
®
WebPACK™
software development systems
and
processor,
®
PCI
Express
®
PIPE Endpoint,
and other
Pb-free packaging options
Automotive
variant
•
Table 1:
Summary of Spartan-3 FPGA Attributes
Equivalent
Logic
Cells
CLB Array
(One CLB = Four Slices)
Rows
Columns
Total
CLBs
Device
System
Gates
Distributed
RAM Bits
(K=1024)
Block RAM
Bits
(K=1024)
Dedicated
Multipliers
DCMs
Maximum
User I/O
Maximum
Differential
I/O Pairs
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
50K
200K
400K
1M
1.5M
2M
4M
5M
1,728
4,320
8,064
17,280
29,952
46,080
62,208
74,880
16
24
32
48
64
80
96
104
12
20
28
40
52
64
72
80
192
480
896
1,920
3,328
5,120
6,912
8,320
12K
30K
56K
120K
208K
320K
432K
520K
72K
216K
288K
432K
576K
720K
1,728K
1,872K
4
12
16
24
32
40
96
104
2
4
4
4
4
4
4
4
124
173
264
391
487
565
633
633
56
76
116
175
221
270
300
300
Notes:
1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
2. These devices are available in Xilinx Automotive versions as described in
Spartan-3 Automotive XA FPGA Family.
© 2003-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-1 (v2.4) June 25, 2008
Product Specification
3
XILINX [ XILINX, INC ]
