R
Platform Flash In-System Programmable Configuration PROMs
XCFxxP Pinouts and Pin Descriptions
XCFxxP VO48/VOG48 and FS48/FSG48 Pin Names and Descriptions
provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48
packages.
Table 14:
XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48)
Pin Name
Boundary-
Scan Order
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
Boundary-
Scan
Function
Data Out
Output Enable
Data Out
Output Enable
Pin Description
48-pin
TSOP
(VO48/
VOG48)
28
48-pin
TFBGA
(FS48/
FSG48)
H6
D0
D1
29
H5
D2
D3
D4
D5
D0 is the DATA output pin to provide data for configuring an
Output Enable FPGA in serial mode.
D0-D7 are the DATA output pins to provide parallel data for
Data Out
configuring a Xilinx FPGA in SelectMap (parallel) mode.
Output Enable The D0 output is set to a high-impedance state during ISPEN
(when not clamped).
Data Out
The D1-D7 outputs are set to a high-impedance state during
Output Enable ISPEN (when not clamped) and when serial mode is selected
for configuration. The D1-D7 pins can be left unconnected
Data Out
when the PROM is used in serial mode.
Output Enable
Data Out
Output Enable
Data Out
Output Enable
Configuration Clock Input. An internal programmable control bit
selects between the internal oscillator and the CLK input pin as
the clock source to control the configuration sequence. Each
rising edge on the CLK input increments the internal address
counter if the CLK input is selected, CE is Low, OE/RESET is
High, BUSY is Low (parallel mode only), and CF is High.
Data Out
32
E5
33
D5
43
C5
44
B5
D6
47
A5
D7
48
A6
CLK
01
Data In
12
B3
04
03
OE/RESET
02
00
CE
Output Enable/Reset (Open-Drain I/O).
When Low, this input holds the address counter reset and the
Data Out
DATA and CLKOUT outputs are placed in a high-impedance
state. This is a bidirectional open-drain pin that is held Low
Output Enable while the PROM completes the internal power-on reset
sequence. Polarity is not programmable.
Data In
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA and CLKOUT outputs are placed in a high-
impedance state.
Data In
11
A3
13
B4
11
10
CF
09
Configuration Pulse (Open-Drain I/O). As an output, this pin
allows the JTAG CONFIG instruction to initiate FPGA
configuration without powering down the FPGA. This is an
open-drain signal that is pulsed Low by the JTAG CONFIG
Data Out
command. As an input, on the rising edge of CF, the current
design revision selection is sampled and the internal address
counter is reset to the start address for the selected revision.
Output Enable If unused, the CF pin must be pulled High using an external
4.7 KΩ pull-up to V
CCO
.
Data In
6
D1
DS123 (v2.13.1) April 3, 2008
Product Specification
39
XILINX [ XILINX, INC ]
