R
XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
Architecture Overview
The XCR22V10 architecture is illustrated in Figure. Twelve
dedicated inputs and ten I/Os provide up to 22 inputs and
ten outputs for creation of logic functions. At the core of the
device is a programmable electrically-erasable AND array
which drives a fixed-OR array. With this structure, the
XCR22V10 can implement up to ten sum-of-products logic
expressions.
Associated with each of the ten OR functions is an I/O mac-
rocell which can be independently programmed to one of
four different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions with either active High or active Low polarity.
44 input lines:
• 24 input lines carry the True and Complement of the
signals applied to the 12 input pins
• 20 additional lines carry the True and Complement
values of feedback or input signals from the ten I/Os
• 132 product terms:
• 120 product terms (arranged in two groups of 8, 10, 12,
14, and 16) used to form logical sums
• Ten output enable terms (one for each I/O)
• One global synchronous preset product term
• One global asynchronous clear product term
At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
which is connected to both the True and Complement of an
input signal will always be FALSE, and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a Don't Care state exists and
that term will always be TRUE.
AND/OR Logic Array
The programmable AND array of the XCR22V10 (shown in
the Logic Diagram,
Figure 1)
is formed by input lines inter-
secting product terms. The input lines and product terms
are used as follows:
CLK/I0
1
11
I1 – I11
PROGRAMMABLE AND ARRAY
(44
×
8
10
12
14
16
132)
16
14
12
10
8
RESET
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060A
Figure 2: Functional Diagram
Variable Product Term Distribution
The XCR22V10 provides 120 product terms to drive the ten
OR functions. These product terms are distributed among
the outputs in groups of 8, 10, 12, 14, and 16 to form logical
sums (see Logic Diagram). This distribution allows opti-
mum use of device resources.
tion of the XCR22V10 to the precise requirements of their
designs.
Macrocell Architecture
Each I/O macrocell, as shown in
Figure 3
consists of a
D-type flip-flop and two signal-select multiplexers. The con-
figuration of each macrocell of the XCR22V10 is deter-
mined by the two EEPROM bits controlling these
multiplexers. These bits determine output polarity, and out-
put type (registered or non-registered). Equivalent circuits
for the macrocell configurations are illustrated in
Figure 4.
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. the ability to configure each
output independently permits users to tailor the configura-
3
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DS048 (v1.1) February 10, 2000
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