XCR3032XL 32 Macrocell CPLD
R
Internal Timing Parameters
(1,2)
-5
Symbol
Buffer Delays
T
IN
T
FIN
T
GCK
T
OUT
T
EN
Input buffer delay
Fast Input buffer delay
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
-
-
-
-
-
0.7
2.2
0.7
1.8
4.5
-
-
-
-
-
1.6
3.0
1.0
2.7
5.0
-
-
-
-
-
2.2
3.1
1.3
3.6
5.7
ns
ns
ns
ns
ns
Parameter
Min.
Max.
Min.
-7
Max.
Min.
-10
Max.
Unit
Internal Register, Product Term, and Combinatorial Delays
T
LDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
PTCK
T
LOGI1
T
LOGI2
Latch transparent delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
Product term clock delay
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
1.0
0.3
2.0
3.0
-
-
-
-
-
-
1.3
-
-
-
-
1.0
2.0
3.5
2.5
2.0
2.5
-
1.0
0.5
2.5
4.5
-
-
-
-
-
-
1.6
-
-
-
-
1.3
2.3
5.0
2.7
2.7
3.2
-
1.2
0.7
3.0
5.5
-
-
-
-
-
-
2.0
-
-
-
-
1.6
2.1
6.0
3.3
3.3
4.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Feedback Delays
T
F
ZIA delay
-
0.5
-
2.9
-
3.5
ns
Time Adders
T
LOGI3
T
UDA
T
SLEW
Fold-back NAND delay
Universal delay
Slew rate limited delay
-
-
-
2.0
1.2
4.0
-
-
-
2.5
2.0
5.0
-
-
-
3.0
2.5
6.0
ns
ns
ns
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See XPLA3 family data sheet (
) for timing model.
4
1-800-255-7778
DS023 (v1.6) June 27, 2002
Preliminary Product Specification
XILINX [ XILINX, INC ]
