Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
R
Revision History
The following table shows the revision history for this document.
Date
03/23/00
08/01/00
Version
1.0
1.1
Initial Xilinx release.
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
•
•
•
•
•
•
•
04/02/01
1.4
•
•
•
In Table 3 (Module 4),
FG676 Fine-Pitch BGA — XCV405E,
the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to
Virtex-E Electrical Characteristics
tables.
Updated speed grade -8 numbers in
Virtex-E Electrical Characteristics
tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of
Absolute Maximum Ratings
(Module 3).
Changed all minimum hold times to –0.4 for
Global Clock Set-Up and Hold for LVTTL
Standard, with DLL
(Module 3).
Revised maximum T
DLLPW
in -6 speed grade for
DLL Timing Parameters
(Module 3).
In
FG676 Fine-Pitch BGA — XCV405E,
pin B19 is no longer labeled as VREF,
and pin G16 is now labeled as VREF.
Updated values in
tables.
Converted data sheet to modularized format. See
below.
Revision
09/19/00
1.2
11/20/00
1.3
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•
•
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Module 1 of 4
4
1-800-255-7778
DS025-1 (v1.4) April 2, 2001
Preliminary Product Specification
XILINX [ XILINX, INC ]
