欢迎访问ic37.com |
会员登录 免费注册
发布采购

XCV600E-6BG432C 参数 Datasheet PDF下载

XCV600E-6BG432C图片预览
型号: XCV600E-6BG432C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -E 1.8 V现场可编程门阵列 [Virtex-E 1.8 V Field Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 5 页 / 89 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XCV600E-6BG432C的Datasheet PDF文件第1页浏览型号XCV600E-6BG432C的Datasheet PDF文件第2页浏览型号XCV600E-6BG432C的Datasheet PDF文件第4页浏览型号XCV600E-6BG432C的Datasheet PDF文件第5页  
R
Virtex™-E 1.8 V Field Programmable Gate Arrays
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Table 2:
Performance for Common Circuit Functions
Function
Register-to-Register
Adder
Pipelined Multiplier
Address Decoder
16:1 Multiplexer
Parity Tree
9
18
36
16
64
8x8
16 x 16
16
64
4.3 ns
6.3 ns
4.4 ns
5.1 ns
3.8 ns
5.5 ns
4.6 ns
3.5 ns
4.3 ns
5.9 ns
Bits
Virtex-E (-7)
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz.
shows performance data for
representative circuits, using worst-case timing parameters.
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
LVPECL
Virtex-E Device/Package Combinations and Maximum I/O
Table 3:
Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
XCV
50E
CS144
PQ240
HQ240
BG352
BG432
BG560
FG256
FG456
FG676
FG680
FG860
FG900
FG1156
512
176
176
176
284
176
312
404
444
512
512
660
660
660
512
660
700
724
804
804
804
512
660
196
260
260
316
316
404
316
404
404
404
404
94
158
XCV
100E
94
158
XCV
200E
94
158
158
158
158
158
XCV
300E
XCV
400E
XCV
600E
XCV
1000E
XCV
1600E
XCV
2000E
XCV
2600E
XCV
3200E
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
1-800-255-7778
Module 1 of 4
3