SP8858
Pin
4
Description
F
PD
= M divider output pulses = RF input frequency
4(MN1A)
when SENSE bit in the programming
word = ‘0’. When SENSE bit = 1, this pin is F
REF
= R divider output pulses = reference input
frequency
4R.
(see Data Entry and Control description and Fig. 6).
F
REF
= R divider output pulses when SENSE bit in the programming word = ‘0’. When SENSE
bit = 1, this pin is F
PD
= M divider output pulses (see Data Entry and Control description and
Fig. 6).
With this pin held high the device is in the power saving standby mode. The serial interface shift
register and data buffers remain active at all times so that the device can still be programmed in
this mode.
Balanced inputs to the RF preamplifier. For single ended operation the signal is AC coupled into
pin 11 with pin 10 decoupled to ground or vice-versa.
The logic level on this input determines which of the two words stored in the internal buffers is used
to reload the A and M dividers at the end of the count cycle. With F1/F2 high the F1 buffer is selected.
Serial data on this line is clocked into a shift register under control of CLOCK and ENABLE.
Clocks the data into the shift register.
Logic high on this pin allows data to be clocked into the shift register and the subsequent falling edge
loads the buffer chosen by the LSBs of the programmed word. The clock input is ignored when
ENABLE is low.
This pin is the input to a buffer amplifier if an external reference signal is provided. Alternatively,
the amplifier provides the active element for a reference oscillator if a quartz crystal is connected
at this point (see Applications).
Leave open circuit if an external reference is used or connect load capacitors for the chosen crystal
(see Applications)
An external resistor connected between this pin and V
CC
sets the charge pump output current. A
multiplication factor can also be programmed into the device (see Table 3)
The phase detector output is a single-ended charge pump sourcing or sinking current to the
inverting input of an external loop filter.
Connected to the non-inverting input of the loop filter to set the DC bias.
A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give
external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time constant and can be
used to vary the sensitivity of the phase lock indicator.
Pre-amp and prescaler supply.
Oscillator supply.
Charge pump supply.
ECL supply.
5
6 (POWER DOWN)
10, 11 (RF INPUT)
13 (F1/F2)
14 (DATA)
15 (CLOCK)
16 (ENABLE)
20 (XTAL 2)
21 (XTAL 1)
24 (RPD)
25 (CP OUTPUT)
26 (CP REF)
27 (LOCK DETECT)
28 (CD)
9 (V
CC
1), 12 (V
EE
1)
18 (V
CC
2), 19 (V
EE
2)
23 (V
CC
3), 2 (V
EE
3)
8 (V
CC
4), 7 (V
EE
4)
Table 1 Pin descriptions
2
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
