eZ80F91 ASSP
Product Specification
9
Table 2. Pin Identification on the eZ80F91 ASSP Device (Continued)
LQFP BGA
Pin No Pin No Symbol
Function
Signal Direction Description
53
54
55
M6
INSTRD
Instruction
Read Indicator Low
Output, Active
INSTRD (with MREQ and RD) indi-
cates the eZ80F91 device is fetching
an instruction from memory. This pin
is in a high-impedance state during
bus acknowledge cycles.
L6
WAIT
WAIT Request Schmitt Trigger
Driving the WAIT pin Low forces the
input, Active Low CPU to wait additional clock cycles for
an external peripheral or external
memory to complete its read or write
operation.
K6
RESET
Reset
Bidirectional,
Active Low
Schmitt Trigger
input or open
drain output
This signal is used to initialize the
eZ80F91, and/or allow the eZ80F91 to
signal when it resets. See the Reset
chapter on page 38 for the timing
details. This Schmitt Trigger input
allows for RC rise times.
56
J6
NMI
Nonmaskable Schmitt Trigger
The NMI input is a higher priority input
Interrupt
input, Active Low, than the maskable interrupts. It is
edge-triggered
interrupt
always recognized at the end of an
instruction, regardless of the state of
the interrupt enable control bits. This
input includes a Schmitt Trigger to
allow for RC rise times.
57
58
M7
L7
BUSREQ
BUSACK
Bus Request
Schmitt Trigger
External devices request the eZ80F91
input, Active Low device to release the memory inter-
face bus for their use by driving this
pin Low.
Bus Acknowl- Output, Active
edge
The eZ80F91 device responds to a
Low on BUSREQ making the address,
data, and control signals high imped-
ance, and by driving the BUSACK line
Low. During bus acknowledge cycles
ADDR[23:0], IORQ, and MREQ are
inputs.
Low
59
60
K7
H6
V
V
Power Supply
Ground
Power Supply.
Ground.
DD
SS
PS027004-0613
P R E L I M I N A R Y
Architectural Overview
ZILOG [ ZILOG, INC. ]
