eZ80F91 ASSP
Product Specification
6
Pin Characteristics
ball BGA package.
Table 2. Pin Identification on the eZ80F91 ASSP Device
LQFP BGA
Pin No Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A1
B1
B2
C3
D4
C1
C2
E5
D2
D1
D3
F6
E1
E2
E3
E4
Symbol
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
V
DD
V
SS
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
V
DD
V
SS
ADDR11
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Signal Direction Description
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Power Supply.
Ground.
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Power Supply.
Ground.
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
PS027004-0613
PRELIMINARY
Architectural Overview
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