eZ80F91 ASSP
Product Specification
41
Low-Power Modes
The eZ80F91 device provides a range of power-saving features. The highest level of
power reduction is provided by SLEEP Mode with all peripherals disabled, including
VBO. The next level of power reduction is provided by the HALT instruction. The most
basic level of power reduction is provided by the clock peripheral power-down registers.
SLEEP Mode
Execution of the CPU’s SLP instruction puts the eZ80F91 device into SLEEP Mode. In
SLEEP Mode, the operating characteristics are:
•
•
•
•
•
The primary crystal oscillator is disabled.
The system clock is disabled.
The CPU is idle.
The Program Counter (PC) stops incrementing.
The 32 kHz crystal oscillator continues to operate and drives the real-time clock and
WDT (if WDT is configured to operate from the 32 kHz oscillator).
The CPU is brought out of SLEEP Mode by any of the following operations:
•
•
•
•
•
A RESET via the external RESET pin driven Low.
A RESET via a real-time clock alarm.
A RESET via a WDT time-out (if running out of the 32 kHz oscillator and configured
to generate a RESET on time-out).
A RESET via execution of a Debug RESET command.
A RESET via the Low-Voltage Brown-Out (VBO) detection circuit, if enabled.
After exiting SLEEP Mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. For more information, see
HALT Mode
Execution of the CPU’s HALT instruction puts the eZ80F91 device into HALT Mode. In
HALT Mode, the operating characteristics are:
•
The primary crystal oscillator is enabled and continues to operate.
PS027004-0613
PRELIMINARY
Low-Power Modes
ZILOG [ ZILOG, INC. ]
