eZ80F91 ASSP
Product Specification
42
•
•
•
•
•
•
•
•
•
The system clock is enabled and continues to operate.
The CPU is idle.
The PC stops incrementing.
The CPU is brought out of HALT Mode by any of the following operations:
A nonmaskable interrupt (NMI).
A maskable interrupt.
A RESET via the external RESET pin driven Low.
A Watchdog Timer time-out (if, configured to generate either an NMI or RESET upon
time-out).
A RESET via execution of a Debug RESET command.
A RESET via the Low-Voltage Brown-Out detection circuit, if enabled.
To minimize current in HALT Mode, the system clock must be gated-off for all unused on-
chip peripherals via the Clock Peripheral Power-Down Registers.
HALT Mode and the EMAC Function
When the CPU is in HALT Mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals can. On receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be blocked to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals are gated off by setting the appropriate bit in the Clock Periph-
eral Power-Down Registers to 1. When powered down, the peripherals are completely dis-
abled. To reenable, the bit in the Clock Peripheral Power-Down Registers must be cleared
to 0.
Additionally, the VBO_OFF bit of CLK_PPD2 is used to disable the VBO detection cir-
cuit and thereby significantly reduce DC current consumption (see
when this function is not required.
Many peripherals features separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
PS027004-0613
PRELIMINARY
Low-Power Modes
ZILOG [ ZILOG, INC. ]
