eZ80L92 MCU
Product Specification
165
ZDI Data Byte
ZCL
ZDA
7
8
9
1
2
3
4
5
6
7
8
9
A0
Read
0/1
D7
D6
D5
D4
D3
D2
D1
D0
1
msb
of DATA
lsb
of DATA
lsb of
Single-Bit
End of Data
or New ZDI
START Signal
ZDI Address Byte Separator
Figure 42. ZDI Single-Byte Data Read Timing
ZDI Block Read
A Block Read operation is initiated the same as a single-byte Read; however, the ZDI
master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to
output data. The ZDI register address counter increments with each Read. If the ZDI regis-
ter address reaches the end of the Read-Only ZDI register address space (20h), the address
stops incrementing. Figure 43 illustrates the ZDI’s Block Read timing.
ZDI Data Bytes
ZCL
7
8
9
1
2
3
7
8
9
1
2
9
ZDA
A0
Read
0/1
D7
D6
D5
D1
D0
0/1
D7
D6
1
msb
of DATA
Byte 1
lsb
of DATA
Byte 1
msb
of DATA
Byte 2
lsb of
Single-Bit
Single-Bit
Byte Separator
ZDI Address Byte Separator
Figure 43. ZDI Block Data Read Timing
Operation of the eZ80L92 During ZDI Break Points
If the ZDI forces the CPU to break, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that can operate auton-
omously from the CPU may continue to operate, if so enabled. For example, the Watch-
Dog Timer and Programmable Reload Timers continue to count during a ZDI break point.
PS013012-1004
P R E L I M I N A R Y
ZiLOG Debug Interface
ZILOG [ ZILOG, INC. ]
