eZ80L92 MCU
Product Specification
207
Figure 50. External Write Timing
20 MHz (ns)
Parameter
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
Description
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Clock Fall to Output DATA Valid Delay
DATA Hold Time from Clock Rise
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
Clock Rise to MREQ Assertion Delay
Clock Rise to MREQ Deassertion Delay
Clock Fall to WR Assertion Delay
Clock Rise to WR Deassertion Delay*
Min.
—
2.4
—
2.4
3.2
2.9
2.8
2.6
1.5
1.4
Max.
10.2
—
6
—
10.3
9.7
9.6
6.9
5.0
3.6
50 MHz (ns)
Min.
—
2.4
—
2.4
3.2
2.9
2.8
2.6
1.5
1.4
Max.
10.2
—
6
—
10.3
9.7
9.6
6.9
5.0
3.6
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR, DATA, CSx,
or MREQ. In certain applications, the deassertion of WR can be concurrent with ADDR, DATA, CSx, or MREQ
when buffering is used off-chip.
PS013012-1004
PRELIMINARY
AC Characteristics
ZILOG [ ZILOG, INC. ]
