eZ80L92 MCU
Product Specification
205
External Memory Read Timing
T
CLK
X
IN
T
1
ADDR[23:0]
T
3
DATA[7:0]
(input)
T
5
CSx
T
7
MREQ
T
9
RD
T
10
T
8
T
6
T
4
T
2
Figure 48. External Memory Read Timing
Table 130. External Read Timing
20 MHz (ns)
Parameter
T
1
T
2
T
3
T
4
T
5
T
6
T
7
Description
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Input DATA Valid to Clock Rise Setup Time
DATA Hold Time from Clock Rise
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
Clock Rise to MREQ Assertion Delay
Min.
—
2.4
1.0
2.4
3.2
2.9
2.8
Max.
10.2
—
—
—
10.3
9.7
9.6
50 MHz (ns)
Min.
—
2.4
1.0
2.4
3.2
2.9
2.8
Max.
10.2
—
—
—
10.3
9.7
9.6
PS013012-1004
PRELIMINARY
AC Characteristics
ZILOG [ ZILOG, INC. ]
