eZ80L92 MCU
Product Specification
213
General Purpose I/O Port Input Sample Timing
pin is sampled on the rising edge of the system clock. The port value is then available to
the CPU on the second rising clock edge following the change of the port value.
T
CLK
System
Clock
Port Value
Changes to 0
GPIO Pin
Input Value
GPIO Input
Data Latch
0 Latched
Into GPIO
Data Register
GPIO Data Register
Value 0 Read
by eZ80
GPIO Data
READ on Data Bus
Figure 55. Port Input Sample Timing
General Purpose I/O Port Output Timing
T
CLK
EXTAL
Port Output
T
1
Figure 56. GPIO Port Output Timing
T
2
PS013012-1004
PRELIMINARY
AC Characteristics
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