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产品型号CDC509PWR的概述

CDC509PWR芯片概述及详细参数分析概述 CDC509PWR是一款高性能的时钟分频器，属于TI（Texas Instruments）公司的一系列时钟管理产品。该芯片被广泛应用于各种数字电路中，尤其是在数据通信和信号处理领域。通过其内部的数字逻辑电路，CDC509PWR能够有效生成较为稳健的时钟信号，实现不同频率之间的转换。 CDC509PWR的设计目标是为了满足高速数据传输及高精度时钟管理的需求。该芯片能够在多种工作模式下运行，为不同的应用场景提供灵活的支持。合适的设计方案，CDC509PWR可以容易地集成到现有的电路中，从而实现高效的时钟生成和分频。详细参数 CDC509PWR具有一系列显著的技术参数，使其成为时钟生成和管理领域的一款理想选手。如下是主要的特性和参数： 1. 供电电压：2.7V-5.5V 2. 最大频率：110MHz 3. 输出类型：CMOS 4. 输出数目...

产品型号CDC509PWR的Datasheet PDF文件预览

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

PW PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Five and One Bank of Four Outputs

AGND

CLK

Separate Output Enable for Each Output

Bank

1Y0

1Y1

1Y2

GND

1Y3

2Y0

2Y1

GND

2Y2

2Y3

External Feedback (FBIN) Pin Is Used to

Synchronize the Outputs to the Clock Input

No External RC Network Required

Operates at 3.3-V V

1Y4

Packaged in Plastic 24-Pin Thin Shrink

Small-Outline Package

FBOUT

FBIN

description

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to

precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It

is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V V and is designed

to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can

be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs

switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low

state.

Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

feedback signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDC509 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

(0:4)

CLK

FBOUT

(0:3)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

functional block diagram

1Y0

1Y1

1Y2

1Y3

1Y4

2Y0

2Y1

2Y2

CLK

PLL

2Y3

FBIN

FBOUT

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(PW)

0°C to 70°C

CDC509PWR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

Clock input. CLK provides the clock signal to be distributed by the CDC509 clock driver. CLK is used

toprovidethereferencesignaltotheintegratedPLLthatgeneratestheclockoutputsignals. CLKmust

have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered

up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the

feedback signal to its reference signal.

CLK

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to

FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is

nominally zero phase error between CLK and FBIN.

FBIN

Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are

disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same

frequency as CLK.

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are

disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same

frequency as CLK.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as

CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.

FBOUT

1Y(0:4)

2Y(0:3)

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via

the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input.

3, 4, 5, 8, 9

16, 17, 20 21

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via

the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input.

Analog power supply. AV

provides the power reference for the analog circuitry. In addition, AV

Power

can be used to bypass the PLL for test purposes. When AV

is strapped to ground, PLL is bypassed

and CLK is buffered directly to the device outputs.

AGND

Ground Analog ground. AGND provides the ground reference for the analog circuitry.

Power Power supply

Ground Ground

GND

2, 10, 15, 22

6, 7, 18, 19

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V

Voltage range applied to any output in the high

or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

Output clamp current, I

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

Continuous current through each V

Maximum power dissipation at T = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W

Storage temperature range, T

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData

Book, literature number SCBD002.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

Supply voltage

3.6

High-level input voltage

Low-level input voltage

Input voltage

0.8

High-level output current

Low-level output current

Operating free-air temperature

–20

°C

NOTE 4: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

I = –18 mA

3 V

–1.2

= –100 µA

= –20 mA

= 100 µA

= 20 mA

MIN to MAX

3 V

–0.2

2.4

MIN to MAX

3 V

0.2

0.55

±5

V = V

or GND

or GND,

3.6 V

µA

‡

V = V

I = 0, Outptus high or low

3.6 V

∆I

One input at V

– 0.6 V,

Other inputs at V

or GND

3.3 V to 3.6 V

3.3 V

500

V = V

or GND

= V or GND

3.3 V

†

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

For I of AV , see Figure 5.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

125

60%

UNIT

Clock frequency

MHz

clock

Input clock duty cycle

40%

Stabilization time

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,

and jitter parameters given in the switching characteristics table are not applicable.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

switching characteristics over recommended ranges of supply voltage and operating free-air

†

temperature, C = 30 pF (see Note 5 and Figures 1 and 2)

= 3.3 V

± 0.165 V

= 3.3 V

± 0.3 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

, reference

(see Figure 3)

66 MHz < CLKIN↑ < 100

phase error

FBIN↑

100...480

340

MHz

, – jitter,

phase error

(see Note 6)

CLKIN↑ = 100 MHz

220

480

‡

Any Y or FBOUT

F(clkin > 66 MHz)

F(clkin ≤ 66 MHz)

F(clkin > 66 MHz)

Any Y or FBOUT

200

100

55%

57%

1.6

sk(o)

Jitter

–100

45%

43%

0.7

(pk-pk)

Duty cycle, reference

(see Figure 4)

1.1

0.8

1.5

1.3

0.5

1.5

†

‡

This parameters are not production tested.

The t specification is only valid for equal loading of all outputs.

sk(o)

NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

6. Phase error does not include jitter. The total phase error is 120 ps to 580 ps for the 5% V range.

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

50% V

From Output

Under Test

2 V

0.4 V

2 V

Output

500

50% V

0.4 V

30 pF

LOAD CIRCUIT FOR OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A.

includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.

C. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

PARAMETER MEASUREMENT INFORMATION

CLKIN

FBIN

phase error

FBOUT

Any Y

sk(o)

Any Y

sk(o)

Figure 2. Phase Error and Skew Calculations

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

TYPICAL CHARACTERISTICS

PHASE ERROR

OUTPUT DUTY CYCLE

CLOCK FREQUENCY

1.2

57%

55%

= 3.3 V

= 25°C

= 30 pF

0.8

0.6

0.4

0.2

53%

51%

49%

47%

45%

43%

–0.2

35 45 55 65 75 85 95 105 115 125 135

110

130

– Clock Frequency – MHz

clk

Figure 3

Figure 4

ANALOG SUPPLY CURRENT

CLOCK FREQUENCY

= 3.3 V

= 25°C

25 35 45 55 65 75 85 95 105 115 125

– Clock Frequency – MHz

clk

Figure 5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CDC509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS576B – JULY 1996 – REVISED JANUARY 1998

MECHANICAL INFORMATION

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,30

0,19

0,65

0,10

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

1,20 MAX

0,05 MIN

PINS **

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/E 08/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

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CDC509PWR产品参数

型号:	CDC509PWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	TSSOP-24
针数：	24
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.69
Is Samacsys：	N
系列：	509
输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	7.8 mm
负载电容（CL）：	30 pF
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.02 A
湿度敏感等级：	1
功能数量：	1
反相输出次数：
端子数量：	24
实输出次数：	9
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.2 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
最小 fmax：	125 MHz
Base Number Matches：	1

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