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产品型号CSD87588N的概述

CSD87588N芯片概述 CSD87588N是一款高效且具有多功能的集成电路，广泛应用于各种功率管理场合，尤其是在DC-DC转换器、工业电源、以及各种消费类电子产品中。其设计目标是为了提高效率，同时减少整体的能源损耗。CSD87588N以其低导通电阻和高开关频率而著称，使其能在高效能的条件下工作，适应多种复杂的电源需求。详细参数根据厂家的数据手册，CSD87588N的关键参数包括： - 导通电阻 (Rds(on))：该芯片在25°C时的导通电阻为1.5 mΩ，确保了其在高电流应用中的低能量损耗。 - 最大输入电压 (Vds)：可以承受的最大电压为20V，适合在多种电源环境下工作。 - 最大电流 (Id)：CSD87588N的最大持续放电电流可达到80A，适合高功耗应用。 - 工作温度范围：芯片的工作温度范围为-40°C至+125°C，能够在极端环境条件下稳定运行。 - 开关频率：...

产品型号CSD87588N的Datasheet PDF文件预览

CSD87588N

www.ti.com

SLPS384A –MARCH 2013–REVISED MAY 2013

Synchronous Buck NexFET™ Power Block II

FEATURES

DESCRIPTION

The CSD87588N NexFET™ power block II is a highly

optimized design for synchronous buck applications

offering high current and high efficiency capability in a

small 5-mm × 2.5-mm outline. Optimized for 5V gate

drive applications, this product offers an efficient and

flexible solution capable of providing a high density

power supply when paired with any 5V gate driver

from an external controller/driver.

•

Half-Bridge Power Block

90% system Efficiency at 20A

Up To 25A Operation

High Density – 5-mm x 2.5-mm LGA Footprint

Double Side Cooling Capability

Ultra Low Profile – 0.48-mm MAX

Optimized for 5V Gate Drive

Low Switching Losses

TEXT ADDED FOR SPACING

ORDERING INFORMATION

Low Inductance Package

RoHS Compliant

Device

Package

Media

Qty

Ship

13-Inch

Reel

Tape and

Reel

CSD87588N

5 x 2.5 LGA

2500

Halogen Free

Pb-Free Terminal Plating

TEXT ADDED FOR SPACING

APPLICATIONS

•

Synchronous Buck Converters

High Current, Low Duty Cycle Applications

–

•

Multiphase Synchronous Buck Converters

POL DC-DC Converters

TEXT ADDED FOR SPACING

TYPICAL POWER BLOCK EFFICIENCY

and POWER LOSS

TYPICAL CIRCUIT

100

V_IN

BOOT

DRVH

V_DD

VDD

GND

V_IN

V_GS= 5V

V_IN= 12V

V_OUT= 1.3V

L_OUT= 0.29µH

f_SW= 500kHz

T_A= 25ºC

V_SW

V_OUT

ENABLE

PWM

ENABLE

PWM

DRVL

P_GND

CSD87588N

Driver IC

Output Current (A)

G001

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NexFET is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CSD87588N

SLPS384A –MARCH 2013–REVISED MAY 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

(1)

T_A= 25°C (unless otherwise noted)

Parameter

Conditions

VALUE

UNIT

MIN

MAX

V_INto P_GND

V_SWto P_GND

Voltage range

V_SWto P_GND(10 ns)

T_Gto V_SW

-20

B_Gto P_GND

(2)

Pulsed Current Rating, I_DM

(3)

Power Dissipation, P_D

Sync FET, I_D= 45A, L = 0.1mH

Control FET, I_D=26A, L = 0.1mH

101

Avalanche Energy E_AS

°C

Operating Junction and Storage Temperature Range, T_J, T_STG

-55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(2) Pulse Duration ≤50 µS. Duty cycle ≤0.01.

(3) Device mounted on FR4 material with 1-inch²(6.45-cm²) Cu.

RECOMMENDED OPERATING CONDITIONS

T_A= 25° (unless otherwise noted)

Parameter

Gate Drive Voltage, V_GS

Conditions

MIN

MAX

UNIT

4.5

Input Supply Voltage, V_IN

Switching Frequency, f_SW

Operating Current

C_BST= 0.1μF (min)

200

1500

kHz

No Airflow

With Airflow

With Airflow + Heat Sink

Operating Temperature, T_J

125

°C

POWER BLOCK PERFORMANCE

T_A= 25° (unless otherwise noted)

Parameter

Conditions

MIN

TYP

MAX

UNIT

V_IN= 12V, V_GS= 5V,

V_OUT= 1.3V, I_OUT= 15A,

f_SW= 500kHz,

(1)

Power Loss, P_LOSS

2.1

L_OUT= 0.29µH, T_J= 25ºC

T_Gto T_GR= 0V

B_Gto P_GND= 0V

V_INQuiescent Current, I_QVIN

µA

(1) Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins and

using a high current 5V driver IC.

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CSD87588N

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SLPS384A –MARCH 2013–REVISED MAY 2013

THERMAL INFORMATION

T_A= 25°C (unless otherwise stated)

THERMAL METRIC

MIN

TYP

MAX UNIT

(1)

Junction to ambient thermal resistance (Min Cu)

Junction to ambient thermal resistance (Max Cu)

170

R_θJA

(2)(1)

°C/W

3.7

(1)

Junction to case thermal resistance (Top of package)

R_θJC

(1)

Junction to case thermal resistance (P_GNDPin)

1.25

(1)

_θJCis determined with the device mounted on a 1-inch²(6.45-cm²), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch

(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. R_θJCis specified by design while R_θJAis determined by the user’s board

design.

(2) Device mounted on FR4 material with 1-inch²(6.45-cm²) Cu.

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SLPS384A –MARCH 2013–REVISED MAY 2013

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ELECTRICAL CHARACTERISTICS

T_A= 25°C (unless otherwise stated)

Q1 Control FET

Q2 Sync FET

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX UNIT

Static Characteristics

BV_DSS

I_DSS

Drain to Source Voltage

V_GS= 0V, I_DS= 250μA

Drain to Source Leakage

Current

V_GS= 0V, V_DS= 24V

100

1.9

100

1.9

μA

Gate to Source Leakage

Current

I_GSS

V_DS= 0V, V_GS= 20

Gate to Source Threshold

Voltage

V_GS(th)

V_DS= V_GS, I_DS= 250μA

1.1

V_GS= 4.5V, I_DS= 15A

V_GS= 10V, I_DS= 15A

V_DS= 10V, I_DS= 15A

10.4

8.0

12.5

9.6

3.5

2.9

4.2

3.5

Drain to Source On

Resistance

R_DS(on)

g_fs

mΩ

Transconductance

Dynamic Characteristics

(1)

C_ISS

Input Capacitance

Output Capacitance

566

341

736

444

2310

682

3000

887

(1)

C_OSS

V_GS= 0V, V_DS= 15V,

f = 1MHz

Reverse Transfer

C_RSS

R_G

10.3

1.2

13.4

2.4

1.1

80.4

2.2

(1)

Capacitance

(1)

Series Gate Resistance

Gate Charge Total (4.5V)

Q_g

3.2

4.1

13.7

17.9

(1)

Gate Charge - Gate to

Drain

Q_gd

Q_gs

0.7

1.4

4.3

V_DS= 15V,

I_DS= 15A

Gate Charge - Gate to

Source

Q_g(th)

Q_OSS

t_d(on)

t_r

Gate Charge at Vth

Output Charge

Turn On Delay Time

Rise Time

0.8

7.0

2.8

18.6

12.1

36.7

20.1

6.3

V_DD= 12V, V_GS= 0V

7.3

31.6

10.2

5.0

V_DS= 15V, V_GS= 4.5V,

I_DS= 15A, R_G= 2Ω

t_d(off)

t_f

Turn Off Delay Time

Fall Time

Diode Characteristics

V_SD

Q_rr

t_rr

Diode Forward Voltage

I_DS= 15A, V_GS= 0V

0.85

12.5

0.78

26.7

Reverse Recovery Charge

Reverse Recovery Time

V_dd= 15V, I_F= 15A,

di/dt = 300A/μs

(1) Specified by design

Max R_θJA= 70°C/W

when mounted on

1 inch²(6.45 cm²) of 2-

oz. (0.071-mm thick)

Cu.

Max R_θJA= 170°C/W

when mounted on

minimum pad area of

2-oz. (0.071-mm thick)

Cu.

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CSD87588N

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SLPS384A –MARCH 2013–REVISED MAY 2013

TYPICAL POWER BLOCK DEVICE CHARACTERISTICS

T_J= 125°C, unless stated otherwise.

1.1

V_IN= 12V

V_GS= 5V

0.9

0.8

0.7

0.6

0.5

V_OUT= 1.3V

f_SW= 500kHz

L_OUT= 0.29µH

V_OUT= 1.3V

f_SW= 500kHz

L_OUT= 0.29µH

11 13 15 17 19 21 23 25

Output Current (A)

−50

−25

100

125

150

Junction Temperature (ºC)

G001

Figure 1. Power Loss vs Output Current

Figure 2. Normalized Power Loss vs Temperature

V_IN= 12V

V_GS= 5V

V_OUT= 1.3V

f_SW= 500kHz

L_OUT= 0.29µH

400LFM

200LFM

100LFM

Nat Conv

100

120

140

Ambient Temperature (ºC)

Board Temperature (ºC)

G001

Figure 3. Safe Operating Area – PCB Horizontal Mount ⁽¹⁾

Figure 4. Typical Safe Operating Area⁽¹⁾

(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with

dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section

for detailed explanation.

TEXT ADDED FOR SPACING

1.35

1.3

3.0

2.6

2.2

1.7

1.3

0.9

0.4

0.0

−0.4

−0.9

1.4

1.35

1.3

3.5

3.0

2.6

2.2

1.7

1.3

0.9

0.4

0.0

−0.4

V_GS= 5V

V_OUT= 1.3V

L_OUT= 0.29µH

f_SW= 500kHz

I_OUT= 25A

1.25

1.2

1.25

1.2

1.15

1.1

1.15

1.1

V_IN= 12V

V_GS= 5V

V_OUT= 1.3V

L_OUT= 0.29µH

I_OUT= 25A

1.05

0.95

0.9

0.95

200 400 600 800 1000 1200 1400 1600 1800

Switching Frequency (kHz)

10 12 14 16 18 20 22 24

Input Voltage (V)

G001

Figure 5. Normalized Power Loss vs Switching Frequency

Figure 6. Normalized Power Loss vs Input Voltage

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SLPS384A –MARCH 2013–REVISED MAY 2013

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TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)

T_J= 125°C, unless stated otherwise.

TEXT ADDED FOR SPACING

1.8

1.6

1.4

1.2

8.6

6.9

5.1

3.4

1.7

1.12

1.1

1.04

0.87

0.69

V_IN= 12V

V_GS= 5V

V_OUT= 1.3V

f_SW= 500kHz

I_OUT= 25A

1.08

1.06

1.04

1.02

0.52

0.35

0.17

V_IN= 12V

V_GS= 5V

f_SW= 500kHz

L_OUT= 0.29µH

I_OUT= 25A

0.98

0.96

0.94

−0.17

−0.35

−0.52

0.8

−1.7

0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

Output Voltage (V)

100 200 300 400 500 600 700 800 900 1000 1100

Output Inductance (nH)

G001

Figure 7. Normalized Power Loss vs. Output Voltage

Figure 8. Normalized Power Loss vs. Output Inductance

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SLPS384A –MARCH 2013–REVISED MAY 2013

TYPICAL POWER BLOCK MOSFET CHARACTERISTICS

T_A= 25°C, unless stated otherwise.

TEXT ADDED FOR SPACING

200

180

160

140

120

100

V_GS= 8.0V

V_GS= 4.5V

V_GS= 4.0V

V_GS= 8.0V

V_GS= 4.5V

V_GS= 4.0V

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8

1.2

V_DS- Drain-to-Source Voltage (V)

G001

Figure 9. Control MOSFET Saturation

TEXT ADDED FOR SPACING

Figure 10. Sync MOSFET Saturation

TEXT ADDED FOR SPACING

100

1000

100

V_DS= 5V

0.1

0.01

0.1

0.001

0.0001

0.00001

0.01

0.001

0.0001

T_C= 125°C

T_C= 25°C

T_C= −55°C

T_C= 125°C

T_C= 25°C

T_C= −55°C

0.5

1.5

2.5

0.5

1.5

2.5

V_GS- Gate-to-Source Voltage (V)

G001

Figure 11. Control MOSFET Transfer

TEXT ADDED FOR SPACING

Figure 12. Sync MOSFET Transfer

TEXT ADDED FOR SPACING

I_D= 15A

V_DS= 15V

I_D= 15A

V_DS= 15V

Q_g- Gate Charge (nC)

G001

Figure 13. Control MOSFET Gate Charge

Figure 14. Sync MOSFET Gate Charge

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SLPS384A –MARCH 2013–REVISED MAY 2013

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TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)

T_A= 25°C, unless stated otherwise.

TEXT ADDED FOR SPACING

10000

1000

100

10000

1000

100

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

C_iss= C_gd+ C_gs

C_oss= C_ds+ C_gd

C_rss= C_gd

V_DS- Drain-to-Source Voltage (V)

G001

Figure 15. Control MOSFET Capacitance

TEXT ADDED FOR SPACING

Figure 16. Sync MOSFET Capacitance

TEXT ADDED FOR SPACING

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

I_D= 250µA

0.9

0.8

0.7

0.6

0.9

0.8

−75

−25

125

175

−75

−25

125

175

T_C- Case Temperature (ºC)

G001

Figure 17. Control MOSFET V_GS(th)

TEXT ADDED FOR SPACING

Figure 18. Sync MOSFET V_GS(th)

TEXT ADDED FOR SPACING

I_D= 15A

T_C= 25°C

T_C= 125ºC

T_C= 25°C

T_C= 125ºC

V_GS- Gate-to- Source Voltage (V)

G001

Figure 19. Control MOSFET R_DS(on)vs V_GS

Figure 20. Sync MOSFET R_DS(on)vs V_GS

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SLPS384A –MARCH 2013–REVISED MAY 2013

TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)

T_A= 25°C, unless stated otherwise.

TEXT ADDED FOR SPACING

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

I_D= 15A

V_GS= 8V

I_D= 15A

V_GS= 8V

0.9

0.8

0.7

0.6

0.9

0.8

0.7

0.6

−75

−25

125

175

−75

−25

125

175

T_C- Case Temperature (ºC)

G001

Figure 21. Control MOSFET Normalized R_DS(on)

TEXT ADDED FOR SPACING

Figure 22. Sync MOSFET Normalized R_DS(on)

TEXT ADDED FOR SPACING

100

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

T_C= 25°C

T_C= 125°C

T_C= 25°C

T_C= 125°C

0.2

0.4

0.6

0.8

0.2

0.4

0.6

0.8 1

V_SD− Source-to-Drain Voltage (V)

G001

Figure 23. Control MOSFET Body Diode

TEXT ADDED FOR SPACING

Figure 24. Sync MOSFET Body Diode

TEXT ADDED FOR SPACING

100

T_C= 25°C

T_C= 125°C

T_C= 25°C

T_C= 125°C

0.01

0.1

0.01

0.1

- Time in Avalanche (ms)

G001

(AV)

Figure 25. Control MOSFET Unclamped Inductive Switching

Figure 26. Sync MOSFET Unclamped Inductive Switching

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The CSD87588N NexFET™ power block is an optimized design for synchronous buck applications using 5V

gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and

highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems

centric environment. System level performance curves such as Power Loss, Safe Operating Area, and

normalized graphs allow engineers to predict the product performance in the actual application.

Power Loss Curves

MOSFET centric parameters such as R_DS(ON)and Q_gdare needed to estimate the loss generated by the devices.

In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss

performance curves. Figure 1 plots the power loss of the CSD87588N as a function of load current. This curve is

measured by configuring and running the CSD87588N as it would be in the final application (see Figure 27).The

measured power loss is the CSD87588N loss and consists of both input conversion loss and gate drive loss.

Equation 1 is used to generate the power loss curve.

(V_INx I_IN) + (V_DDx I_DD) – (V_{SW_AVG}x I_OUT) = Power Loss

(1)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C

under isothermal test conditions.

Safe Operating Curves (SOA)

The SOA curves in the CSD87588N data sheet provides guidance on the temperature boundaries within an

operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the

temperature and airflow conditions required for a given load current. The area under the curve dictates the safe

operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x

3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thickness.

Normalized Curves

The normalized curves in the CSD87588N data sheet provides guidance on the Power Loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change is system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is

subtracted from the SOA curve.

Input Current (I_IN)

V_IN

BOOT

DRVH

V_DD

VDD

V_IN

Input Voltage (V_IN)

Gate Drive

Voltage (V_DD)

ENABLE

PWM

Output Current (I_OUT

)

V_SW

V_OUT

PWM

DRVL

P_GND

GND

Averaged Switch

V Node Voltage

Averaging

Circuit

CSD873588N

Driver IC

(V_{SW_AVG}

)

Figure 27. Typical Application

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SLPS384A –MARCH 2013–REVISED MAY 2013

Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though

the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following

procedure will outline the steps the user should take to predict product performance for any set of system

conditions.

Design Example

Operating Conditions:

•

Output Current = 15A

Input Voltage = 7V

Output Voltage = 1V

Switching Frequency = 800kHz

Inductor = 0.2µH

Calculating Power Loss

•

Power Loss at 15A = 2.75W (Figure 1)

Normalized Power Loss for input voltage ≈ 1.03 (Figure 6)

Normalized Power Loss for output voltage ≈ 0.94 (Figure 7)

Normalized Power Loss for switching frequency ≈ 1.08 (Figure 5)

Normalized Power Loss for output inductor ≈ 1.03 (Figure 8)

Final calculated Power Loss = 2.75W x 1.05 x 0.95 x 1.05 x 1.05 ≈ 3.02W

Calculating SOA Adjustments

•

SOA adjustment for input voltage ≈ 0.3ºC (Figure 6)

SOA adjustment for output voltage ≈ -0.5ºC (Figure 7)

SOA adjustment for switching frequency ≈ 0.7ºC (Figure 5)

SOA adjustment for output inductor ≈ 0.3ºC (Figure 8)

Final calculated SOA adjustment = 0.3 + (-0.5) + 0.7 + 0.3 ≈ 0.8ºC

In the design example above, the estimated power loss of the CSD87588N would increase to 3.02W. In addition,

the maximum allowable board and/or ambient temperature would have to decrease by 0.8ºC. Figure 28

graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 0.8ºC. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

Figure 28. Power Block SOA

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RECOMMENDED PCB DESIGN OVERVIEW

There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and

Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief

description on how to address each parameter is provided.

Electrical Performance

The CSD87588N has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

•

The placement of the input capacitors relative to VIN and PGND pins of CSD87588N device should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 5).

The example in Figure 5 uses 1x10nF 0402 25V and 4 x 10μF 1206 25V ceramic capacitors (TDK Part #

C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an

appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power

Stage C21, C5, C8, C19, and C18 should follow in order.

•

The switching node of the output inductor should be placed relatively close to the Power Block II CSD87588N

VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction

losses and actually reduce the switching noise level.see Figure 29

(1)

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

Thermal Performance

The CSD87588N has the ability to utilize the PGND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

Figure 29. Recommended PCB Layout (Top Down View)

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CSD87588N

www.ti.com

SLPS384A –MARCH 2013–REVISED MAY 2013

MECHANICAL DATA

CSD87588N Package Dimensions

Table 1. Pin Configuration

Position

Pin 1

Designation

V_IN

Pin 2

Pin 3

P_GND

Pin 4

Pin 5

V_SW

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CSD87588N

SLPS384A –MARCH 2013–REVISED MAY 2013

www.ti.com

Land Pattern Recommendation

1.250 REF PKG

0.858

0.000

0.238

0.538

0.238

0.538

0.858

1.250 REF PKG

PACKAGE

OUTLINE

Text For Spacing

Stencil Recommendation (100 µm)

Text For Spacing .

Text For Spacing

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CSD87588N

www.ti.com

SLPS384A –MARCH 2013–REVISED MAY 2013

Stencil Recommendation (125 µm)

Text

For

Spacing

For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through

PCB Layout Techniques.

Text For Spacing

Pin Drawing

87588N

TI YMS

LLLL E

Text For Spacing

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CSD87588N

SLPS384A –MARCH 2013–REVISED MAY 2013

www.ti.com

CSD87588N Embossed Carrier Tape Dimensions

(1) Pin 1 will be oriented in the top left quadrant of the tape enclosure (closest to the carrier tape sprocket holes).

spacer

REVISION HISTORY

Changes from Original (March 2013) to Revision A

Page

•

Changed R_θJC-PCBTo: R_θJCin the THERMAL INFORMATION table ...................................................................................... 3

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PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

CSD87588N

ACTIVE

PTAB

MPA

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-55 to 150

87588N

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CSD87588N

PTAB

MPA

2500

330.0

12.4

2.8

5.3

0.55

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

PTAB MPA

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

CSD87588N

2500

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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CSD87588N产品参数

型号:	CSD87588N
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	LGA,
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8541.29.00.95
Factory Lead Time：	8 weeks
风险等级：	1.68
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制技术：	PULSE WIDTH MODULATION
JESD-30 代码：	R-XBGA-N5
JESD-609代码：	e4
长度：	5 mm
湿度敏感等级：	1
功能数量：	1
封装主体材料：	UNSPECIFIED
封装代码：	LGA
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260
座面最大高度：	0.4 mm
最大供电电流 (Isup)：	25 mA
表面贴装：	YES
温度等级：	MILITARY
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	2.5 mm
Base Number Matches：	1

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