CY7C199-15PC全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号CY7C199-15PC的概述

CY7C199-15PC 概述 CY7C199-15PC 是由赛普拉斯半导体（Cypress Semiconductor）公司生产的一款静态随机存取存储器（SRAM）。作为一种高性能存储解决方案，该芯片以其快速的数据访问速度和易于使用的接口特点，被广泛应用于各种电子设备中。这款 SRAM 具有较高的存储容量和较短的读写延迟，适用于对速度要求较高的应用场合。 CY7C199-15PC 的存储单元采用了高密度的 CMOS 技术，提供了高效的功耗管理与出色的集成度。此外，它的设计考虑了良好的输入输出性能，旨在满足现代电子设备在数据存储与处理方面的需求。详细参数 CY7C199-15PC 具有如下主要参数： 1. 存储容量：64K x 1 位 2. 访问时间：15 纳秒（典型读写时间） 3. 工作电压：5V ± 10% 4. 工作温度范围：-40°C 至 +85°C 5. 封装类型：DIP-...

产品型号CY7C199-15PC的Datasheet PDF文件预览

CY7C199

32K x 8 Static RAM

is provided by an active LOW Chip Enable (CE) and active

LOW Output Enable (OE) and three-state drivers. This device

has an automatic power-down feature, reducing the power

consumption by 81% when deselected. The CY7C199 is in the

standard 300-mil-wide DIP, SOJ, and LCC packages.

Features

• High speed

— 10 ns

• Fast t_DOE

An active LOW Write Enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location

addressed by the address present on the address pins (A₀

through A₁₄). Reading the device is accomplished by selecting

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

• CMOS for optimum speed/power

• Low active power

— 467 mW (max, 12 ns “L” version)

• Low standby power

— 0.275 mW (max, “L” version)

• 2V data retention (“L” version only)

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and Write Enable

(WE) is HIGH. A die coat is used to improve alpha immunity.

Functional Description

The CY7C199 is a high-performance CMOS static RAM

organized as 32,768 words by 8 bits. Easy memory expansion

Logic Block Diagram

Pin Configurations

DIP / SOJ / SOIC

LCC

Top View

2 1 2827

I/O

INPUT BUFFER

I/O

1314151617

I/O

GND

1024 x 32 x 8

ARRAY

I/O

GND

I/O

TSOP I

Top View

(not to scale)

POWER

DOWN

COLUMN

DECODER

I/O

Selection Guide

7C199 7C199

7C199 7C199 7C199 7C199 7C199 7C199

-8

-10

-12

-15

-20

-25

-35

-45

Unit

Maximum Access Time

Maximum Operating Current

120

110

0.5

0.05

160

155

150

140

Maximum CMOS Standby Current

0.5

0.05

Shaded area contains advance information.

Cypress Semiconductor Corporation

Document #: 38-05160 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 7, 2003

CY7C199

Output Current into Outputs (LOW)............................. 20 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage to Ground Potential

(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V

Range

Commercial

Industrial

Military

Ambient Temperature^[2]

V_CC

0°C to +70°C

5V ± 10%

DC Voltage Applied to Outputs

–40°C to +85°C

in High-Z State^[1]....................................–0.5V to V_CC+ 0.5V

DC Input Voltage^[1].................................–0.5V to V_CC+ 0.5V

–55°C to +125°C

Electrical Characteristics Over the Operating Range (-8, -10, -12, -15)^[3]

7C199-8

7C199-10

7C199-12

7C199-15

Parameter

V_OH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

V_CC= Min., I_OH=–4.0 mA

V_CC= Min., I_OL=8.0 mA

Min. Max. Min. Max. Min. Max. Min. Max. Unit

2.4

V_OL

0.4

2.2 V_CC2.2 V_CC2.2 V_CC2.2 V_CC

+0.3V +0.3V +0.3V +0.3V

–0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8

0.4

V_IH

V_IL

I_IX

Input LOW Voltage

Input Load Current

GND < V_I< V_CC

–5

µA

I_OZ

Output Leakage Current GND < V_O< V_CC, Output

Disabled

I_CC

V_CCOperating Supply

Current

V_CC= Max.,

I_OUT= 0 mA,

f = f_MAX= 1/t_RC

Com’l

120

110

160

155 mA

100 mA

180 mA

Mil

I_SB1

Automatic CE

Power-down Current— V_IH, V_IN> V_IHor

TTL Inputs

Max. V_CC, CE >

Com’l

V_IN< V_IL, f = f_MAX

I_SB2

Automatic CE

Power-down Current— CE > V_CC– 0.3V

CMOS Inputs

Max. V_CC

Com’l

0.5

0.05

0.05 mA

15 mA

V_IN> V_CC– 0.3V

or V_IN< 0.3V, f = 0

Mil

[3]

Electrical Characteristics Over the Operating Range (-20, -25, -35, -45)

7C199-20 7C199-25 7C199-35

7C199-45

Parameter

V_OH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

Min. Max. Min. Max. Min. Max. Min. Max. Unit

V_CC= Min., I_OH= –4.0 mA 2.4

2.4

2.2

V_OL

V_CC= Min., I_OL= 8.0 mA

0.4

2.2 V_CC2.2 V_CC2.2 V_CC

+0.3V +0.3V +0.3V

–0.5 0.8 -0.5 0.8 -0.5 0.8

0.4

V_IH

V_CC

+0.3V

V_IL

I_IX

Input LOW Voltage

Input Load Current

-0.5

–5

0.8

GND < V_I< V_CC

–5

µA

I_OZ

Output Leakage Current GND < V_I< V_CC, Output

Disabled

–5

I_CC

V_CCOperating Supply

Current

V_CC= Max.,

I_OUT= 0 mA,

f = f_MAX= 1/t_RC

Com’l

150

140

140 mA

70 mA

Mil

170

150

150 mA

Shaded area contains advance information.

Notes:

V_IL(min.) = –2.0V for pulse durations of less than 20 ns.

2. T_Ais the “instant on” case temperature.

3. See the last page of this specification for Group A subgroup testing information.

Document #: 38-05160 Rev. *A

Page 2 of 13

CY7C199

Electrical Characteristics Over the Operating Range (-20, -25, -35, -45) (continued)^[3]

7C199-20 7C199-25 7C199-35

7C199-45

Parameter

Description

Test Conditions

Min. Max. Min. Max. Min. Max. Min. Max. Unit

I_SB1

Automatic CE

Power-down Current—

TTL Inputs

Max. V_CC,CE> V_IH, Com’l

V_IN> V_IHorV_IN< V_IL,

f = f_MAX

I_SB2

Automatic CE

Power-down Current—

CMOS Inputs

Max. V_CC

CE > V_CC– 0.3V

_IN> V_CC– 0.3V or

Com’l

0.05

0.05 µA

Mil

V_IN< 0.3V, f=0

Capacitance^{[4 ]}

Parameter

Description

Test Conditions

Max.

Unit

C_IN

Input Capacitance

Output Capacitance

T_A= 25°C, f = 1 MHz,

V_CC= 5.0V

C_OUT

AC Test Loads and Waveforms^[5]

R1 481Ω

ALL INPUT PULSES

90%

OUTPUT

3.0V

GND

90%

10%

255 Ω

255Ω

30 pF

5 pF

≤t

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT

167 Ω

OUTPUT

1.73V

Data Retention Characteristics Over the Operating Range (L-version only)

Parameter

V_DR

I_CCDR

Description

V_CCfor Data Retention

Data Retention Current

Conditions^[6]

Min.

Max.

Unit

2.0

Com’l

V_CC= V_DR= 2.0V, CE > V_CC

0.3V, V_IN> V_CC–0.3V or V_IN

0.3V

–

µA

Com’l L

[4]

t_CDR

Chip Deselect to Data Retention Time

Operation Recovery Time

[5]

t_R

200

µs

Data Retention Waveform

DATA RETENTION MODE

3.0V

> 2V

CDR

Note:

4. Tested initially and after any design or process changes that may affect these parameters.

5. t_R< 3 ns for the -12 and the -15 speeds. t_R< 5 ns for the -20 and slower speeds

6. No input may exceed V_CC+ 0.5V.

Document #: 38-05160 Rev. *A

Page 3 of 13

CY7C199

[3, 7]

Switching Characteristics Over the Operating Range (-8, -10, -12, -15)

7C199-8

7C199-10

7C199-12

Min. Max.

7C199-15

Min. Max.

Parameter

Read Cycle

t_RC

Description

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

t_AA

Address to Data Valid

Data Hold from Address Change

CE LOW to Data Valid

OE LOW to Data Valid

OE LOW to Low-Z^[8]

OE HIGH to High-Z^{[8, 9]}

CE LOW to Low-Z^[8]

CE HIGH to High-Z^[8,9]

CE LOW to Power-up

CE HIGH to Power-down

t_OHA

t_ACE

t_DOE

4.5

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

t_PD

Write Cycle^{[10, 11]}

t_WC

t_SCE

t_AW

Write Cycle Time

CE LOW to Write End

Address Set-up to Write End

Address Hold from Write End

Address Set-up to Write Start

WE Pulse Width

t_HA

t_SA

t_PWE

t_SD

Data Set-up to Write End

Data Hold from Write End

WE LOW to High-Z^[9]

t_HD

t_HZWE

t_LZWE

WE HIGH to Low-Z^[8]

Switching Characteristics Over the Operating Range (-20, -25, -35, -45)^{[3, 7]}

7C199-20 7C199-25

Min. Max.

7C199-35

7C199-45

Parameter

Read Cycle

t_RC

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

t_AA

Address to Data Valid

Data Hold from Address Change

CE LOW to Data Valid

OE LOW to Data Valid

OE LOW to Low-Z^[8]

OE HIGH to High-Z^{[8, 9]}

CE LOW to Low-Z^[8]

t_OHA

t_ACE

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

CE HIGH to High-Z^{[8, 9]}

CE LOW to Power-up

Shaded area contains advance information.

Notes:

7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,

input pulse levels of 0 to 3.0V, and output loading of the specified I_OL/I_OHand 30-pF load capacitance.

8. At any given temperature and voltage condition, t_HZCEis less than t_LZCE, t_HZOEis less than t_LZOE, and t_HZWEis less than t_LZWEfor any given device.

9. t_HZOE, t_HZCE, and t_HZWEare specified with C_L= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWEand t_SD

Document #: 38-05160 Rev. *A

Page 4 of 13

CY7C199

Switching Characteristics Over the Operating Range (-20, -25, -35, -45)^{[3, 7]}

7C199-20 7C199-25

Min. Max. Min. Max.

20 20

7C199-35

Min. Max.

7C199-45

Min. Max.

Parameter

t_PD

Description

Unit

CE HIGH to Power-down

Write Cycle^[10,11]

t_WC

t_SCE

t_AW

Write Cycle Time

CE LOW to Write End

Address Set-up to Write End

Address Hold from Write End

Address Set-up to Write Start

WE Pulse Width

t_HA

t_SA

t_PWE

t_SD

Data Set-up to Write End

Data Hold from Write End

WE LOW to High-Z^[9]

t_HD

t_HZWE

t_LZWE

WE HIGH to Low-Z^[8]

Switching Waveforms

Read Cycle No. 1^{[12, 13]}

ADDRESS

OHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 ^{[13, 14]}

ACE

HZOE

DOE

HZCE

LZOE

HIGH

IMPEDANCE

HIGH IMPEDANCE

DATA OUT

DATA VALID

LZCE

ICC

SUPPLY

CURRENT

50%

ISB

Notes:

12. Device is continuously selected. OE, CE = V_IL.

13. WE is HIGH for read cycle.

14. Address valid prior to or coincident with CE transition LOW.

Document #: 38-05160 Rev. *A

Page 5 of 13

CY7C199

Switching Waveforms (continued)

Write Cycle No. 1 (WE Controlled)^{[10, 15, 16]}

ADDRESS

PWE

DATA VALID

DATA I/O

HZOE

Write Cycle No. 2 (CE Controlled)^{[10, 15, 16]}

ADDRESS

SCE

DATA I/O

DATA VALID

Write Cycle No. 3 (WE Controlled OE LOW)^{[11, 16]}

ADDRESS

DATA I/O

DATA VALID

LZWE

HZWE

Notes:

15. Data I/O is high impedance if OE = V_IH

16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 38-05160 Rev. *A

Page 6 of 13

CY7C199

Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

NORMALIZED SUPPLY CURRENT

vs. SUPPLY

VOLTAGE

120

100

1.4

1.2

1.4

1.2

1.0

0.8

0.6

1.0

0.8

0.6

=5.0V

T =25°C

=5.0V

T =25°C

=5.0V

0.4

0.2

0.0

0.2

0.0

–55

125

0.0

1.0

2.0

3.0

4.0

4.5

5.0

5.5

6.0

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME

vs. AMBIENT TEMPERATURE

OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE

NORMALIZED ACCESS TIME

vs. SUPPLY VOLTAGE

140

120

1.6

1.4

1.3

1.2

100

1.2

1.0

1.1

1.0

T =25°C

=5.0V

T =25°C

=5.0V

0.8

0.9

0.8

0.6

–55

0.0

1.0

2.0

3.0

4.0

125

4.0

4.5

5.0

5.5

6.0

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

TYPICALPOWER-ON CURRENT

vs.SUPPLY VOLTAGE

TYPICAL ACCESS TIMECHANGE

vs. OUTPUT LOADING

NORMALIZED I vs. CYCLETIME

3.0

2.5

2.0

1.5

30.0

25.0

20.0

15.0

1.25

1.00

0.75

0.50

=5.0V

T =25°C

=0.5V

=4.5V

1.0

0.5

10.0

5.0

T =25°C

0.0

1.0

2.0

3.0

4.0

5.0

200 400

600 800 1000

SUPPLY VOLTAGE (V)

CAPACITANCE (pF)

CYCLE FREQUENCY (MHz)

Truth Table

Inputs/Outputs

High Z

Mode

Power

Deselect/Power-down

Read

Standby (I_SB

Active (I_CC

)

Data Out

Data In

High Z

)

Write

)

Deselect, Output disabled

)

Document #: 38-05160 Rev. *A

Page 7 of 13

CY7C199

Ordering Information

Speed

Package

Name

Operating

Range

(ns)

Ordering Code

Package Type

28-Lead Molded SOJ

CY7C199-8VC

V21

Z28

V21

Z28

V21

Z28

V21

Z28

V21

Z28

V21

Z28

P21

V21

Z28

P21

V21

Z28

V21

Z28

V21

Z28

P21

V21

Z28

P21

V21

Z28

V21

Z28

D22

L54

D22

L54

P21

V21

Z28

P21

V21

Z28

V21

Z28

D22

L54

D22

L54

Commercial

Industrial

CY7C199-8ZC

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

CY7C199L-8VC

CY7C199L-8ZC

CY7C199-10VC

CY7C199-10ZC

CY7C199L-10VC

CY7C199L-10ZC

CY7C199-10VI

CY7C199-10ZI

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

CY7C199L-10VI

CY7C199L-10ZI

CY7C199-12PC

CY7C199-12VC

CY7C199-12ZC

CY7C199L-12PC

CY7C199L-12VC

CY7C199L-12ZC

CY7C199-12VI

CY7C199-12ZI

28-Lead Thin Small Outline Package

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOJ

Commercial

28-Lead Thin Small Outline Package

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

Industrial

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

CY7C199L-12VI

CY7C199L-12ZI

CY7C199-15PC

CY7C199-15VC

CY7C199-15ZC

CY7C199L-15PC

CY7C199L-15VC

CY7C199L-15ZC

CY7C199-15VI

CY7C199-15ZI

28-Lead Thin Small Outline Package

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOJ

Commercial

28-Lead Thin Small Outline Package

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

Industrial

Military

28-Lead Thin Small Outline Package

28-Lead (300-Mil) CerDIP

CY7C199-15DMB

CY7C199-15LMB

CY7C199L-15DMB

CY7C199L-15LMB

CY7C199-20PC

CY7C199-20VC

CY7C199-20ZC

CY7C199L-20PC

CY7C199L-20VC

CY7C199L-20ZC

CY7C199-20VI

CY7C199-20ZI

28-Pin Rectangular Leadless Chip Carrier

28-Lead (300-Mil) CerDIP

28-Pin Rectangular Leadless Chip Carrier

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOJ

Commercial

28-Lead Thin Small Outline Package

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOJ

Industrial

Military

28-Lead Thin Small Outline Package

28-Lead (300-Mil) CerDIP

CY7C199-20DMB

CY7C199-20LMB

CY7C199L-20DMB

CY7C199L-20LMB

28-Pin Rectangular Leadless Chip Carrier

28-Lead (300-Mil) CerDIP

28-Pin Rectangular Leadless Chip Carrier

Shaded area contains advance information. Contact your Cypress sales representative for availability

Document #: 38-05160 Rev. *A

Page 8 of 13

CY7C199

Ordering Information (continued)

Speed

Package

Name

Operating

Range

(ns)

Ordering Code

CY7C199-25PC

Package Type

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOIC

P21

S21

V21

Z28

S21

V21

Z28

D22

L54

P21

S21

V21

Z28

S21

V21

Z28

D22

L54

D22

L54

Commercial

CY7C199-25SC

CY7C199-25VC

CY7C199-25ZC

CY7C199-25SI

CY7C199-25VI

CY7C199-25ZI

CY7C199-25DMB

CY7C199-25LMB

CY7C199-35PC

CY7C199-35SC

CY7C199-35VC

CY7C199-35ZC

CY7C199-35SI

CY7C199-35VI

CY7C199-35ZI

CY7C199-35DMB

CY7C199-35LMB

CY7C199-45DMB

CY7C199-45LMB

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOIC

Industrial

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead (300-Mil) CerDIP

Military

28-Pin Rectangular Leadless Chip Carrier

28-Lead (300-Mil) Molded DIP

28-Lead Molded SOIC

Commercial

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead Molded SOIC

Industrial

28-Lead Molded SOJ

28-Lead Thin Small Outline Package

28-Lead (300-Mil) CerDIP

Military

28-Pin Rectangular Leadless Chip Carrier

28-Lead (300-Mil) CerDIP

28-Pin Rectangular Leadless Chip Carrier

Shaded area contains advance information. Contact your Cypress sales representative for availability

MILITARY SPECIFICATIONS

Group A Subgroup Testing

DC Characteristics

Switching Characteristics

Parameter

Subgroups

1, 2, 3

Parameter

Read Cycle

t_RC

t_AA

Subgroups

V_OH

V_OL

V_IH

1, 2, 3

7, 8, 9, 10, 11

V_ILMax.

I_IX

t_OHA

t_ACE

t_DOE

Write Cycle

t_WC

I_OZ

I_CC

I_SB1

I_SB2

7, 8, 9, 10, 11

t_AA

t_AW

t_HA

t_SA

t_PWE

t_SD

t_HD

Document #: 38-05160 Rev. *A

Page 9 of 13

CY7C199

Package Diagrams

28-pin (300-Mil) CerDIP D22

MIL-STD-1835 D-15 Config. A

51-80032-**

28-pin Rectangular Leadless Chip Carrier L54

MIL-STD-1835C-11A

51-80067-**

Document #: 38-05160 Rev. *A

Page 10 of 13

CY7C199

Package Diagrams (continued)

28-pin (300-Mil) Molded DIP P21

51-85014-B

28-pin (300-Mil) Molded SOIC S21

51-85026-A

Document #: 38-05160 Rev. *A

Page 11 of 13

CY7C199

Package Diagrams (continued)

28-pin (300-Mil) Molded SOJ V21

51-85031-B

28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28

51-85071-*G

All products and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05160 Rev. *A

Page 12 of 13

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C199

Document History Page

Document Title: CY7C199 32K x 8 Static RAM

Document Number: 38-05160

Issue

Date

Orig. of

Change

REV.

ECN NO.

109971

121730

Description of Change

Change from Spec number: 38-00239 to 38-05160

Updated Product Offering table.

10/28/01

01/09/02

SZV

DFP

Document #: 38-05160 Rev. *A

Page 13 of 13

CY7C199-15PC相关文章

配单直通车

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CY7C199-15PC产品参数

型号:	CY7C199-15PC
是否无铅：	含铅
是否Rohs认证：	不符合
生命周期：	Contact Manufacturer
零件包装代码：	DIP
包装说明：	DIP,
针数：	28
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.41
风险等级：	5.68
Is Samacsys：	N
最长访问时间：	15 ns
其他特性：	AUTOMATIC POWER-DOWN
JESD-30 代码：	R-PDIP-T28
长度：	35.4965 mm
内存密度：	262144 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	8
功能数量：	1
端子数量：	28
字数：	32768 words
字数代码：	32000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	32KX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	4.826 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm
Base Number Matches：	1

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