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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • DS90LV001TMX 现货库存
  • 数量2500 
  • 厂家TI 
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  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • DS90LV001TMX 现货库存
  • 数量2500 
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     该会员已使用本站12年以上
  • DS90LV001TMX/NOPB 现货库存
  • 数量50600 
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     该会员已使用本站15年以上
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  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
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  • 数量660000 
  • 厂家Texas Instruments(德州仪器) 
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     该会员已使用本站7年以上
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     该会员已使用本站11年以上
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  • 数量25000 
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     该会员已使用本站2年以上
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  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • DS90LV001TMX
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     该会员已使用本站13年以上
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     该会员已使用本站2年以上
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     该会员已使用本站4年以上
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  • 数量15000 
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     该会员已使用本站2年以上
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  • 数量22500 
  • 厂家TI(德州仪器) 
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  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
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  • 数量5000 
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     该会员已使用本站11年以上
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  • 数量2500 
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     该会员已使用本站13年以上
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     该会员已使用本站14年以上
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     该会员已使用本站7年以上
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     该会员已使用本站13年以上
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  • 数量5000 
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     该会员已使用本站13年以上
  • DS90LV001TMX
  • 数量865000 
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     该会员已使用本站12年以上
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  • 数量89630 
  • 厂家TI/德州仪器 
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     该会员已使用本站10年以上
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     该会员已使用本站7年以上
  • DS90LV001TMX/NOPB
  • 数量4505 
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  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
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  • 数量8800 
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  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
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  • 数量10000 
  • 厂家TI/德州仪器 
  • 封装8-SOIC 
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  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
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  • 数量65400 
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     该会员已使用本站12年以上
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  • 数量5321 
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  • 深圳市高捷芯城科技有限公司

     该会员已使用本站11年以上
  • DS90LV001TMX/NOPB
  • 数量9555 
  • 厂家TI(德州仪器) 
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • DS90LV001TMX/NOPB
  • 数量35 
  • 厂家TI/德州仪器 
  • 封装NA/ 
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  • 深圳市卓越微芯电子有限公司

     该会员已使用本站12年以上
  • DS90LV001TMX
  • 数量6500 
  • 厂家NSC 
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
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  • 数量28112 
  • 厂家TI/NS 
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     该会员已使用本站16年以上
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  • 数量12500 
  • 厂家TI/德州仪器 
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     该会员已使用本站5年以上
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  • 数量13500 
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     该会员已使用本站15年以上
  • DS90LV001TMX/NOPB
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装8-SOIC 
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站12年以上
  • DS90LV001TMX
  • 数量12300 
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  • 北京齐天芯科技有限公司

     该会员已使用本站15年以上
  • DS90LV001TMX/NOPB
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装8-SOIC 
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     该会员已使用本站14年以上
  • DS90LV001TMX
  • 数量12736 
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     该会员已使用本站17年以上
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     该会员已使用本站16年以上
  • DS90LV001TMX
  • 数量1000 
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  • 封装SOP-8 
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     该会员已使用本站11年以上
  • DS90LV001TMX
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  • 厂家TI-德州仪器 
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     该会员已使用本站15年以上
  • DS90LV001TMX/NOPB
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产品型号DS90LV001TMX的概述

DS90LV001TMX芯片概述 DS90LV001TMX是一款高性能的低压差分信号(LVDS)发送器,广泛用于高速数据传输应用。该芯片的主要设计目标是为高达1.0 Gbps的数据传输提供可靠的解决方案,尤其在信号的完整性和传输距离方面具有显著优势。DS90LV001TMX能够有效地降低电磁干扰(EMI)并提高信号传输的抗干扰能力,使其适用于各种工业和商业应用,如视频监控、数据采集系统以及高清晰度显示设备。 DS90LV001TMX的详细参数 DS90LV001TMX的主要技术参数包括: - 工作电压:3.3V - 差分信号输出幅度:具有较低的电源电压,信号输出范围为250 mV至600 mV。 - 数据传输速率:最高支持1.0 Gbps的数据传输速率,适应高速应用的需求。 - 工作温度范围:-40°C至+85°C,能够在恶劣环境下正常工作。 - 供电电流:通常在15 mA左右,具备良...

产品型号DS90LV001TMX的Datasheet PDF文件预览

DS90LV001  
www.ti.com  
SNLS067E JANUARY 2001REVISED APRIL 2013  
DS90LV001 800 Mbps LVDS Buffer  
Check for Samples: DS90LV001  
1
FEATURES  
DESCRIPTION  
The DS90LV001 LVDS-LVDS Buffer takes an LVDS  
input signal and provides an LVDS output signal. In  
many large systems, signals are distributed across  
backplanes, and one of the limiting factors for system  
speed is the "stub length" or the distance between  
the transmission line and the unterminated receivers  
on individual cards. Although it is generally  
recognized that this distance should be as short as  
possible to maximize system performance, real-world  
packaging concerns often make it difficult to make the  
stubs as short as the designer would like.  
2
Single +3.3 V Supply  
LVDS Receiver Inputs Accept LVPECL Signals  
TRI-STATE Outputs  
Receiver Input Threshold < ±100 mV  
Fast Propagation Delay of 1.4 ns (Typ)  
Low Jitter 800 Mbps Fully Differential Data  
Path  
100 ps (Typ) of pk-pk Jitter with PRBS = 2231  
Data Pattern at 800 Mbps  
The DS90LV001, available in the WSON package,  
will allow the receiver to be placed very close to the  
main transmission line, thus improving system  
performance.  
Compatible with ANSI/TIA/EIA-644-A LVDS  
Standard  
8 pin SOIC and Space Saving (70%) WSON  
Package  
A
wide input dynamic range will allow the  
Industrial Temperature Range  
DS90LV001 to receive differential signals from  
LVPECL as well as LVDS sources. This will allow the  
device to also fill the role of an LVPECL-LVDS  
translator.  
An output enable pin is provided, which allows the  
user to place the LVDS output in TRI-STATE.  
The DS90LV001 is offered in two package options,  
an 8 pin WSON and SOIC.  
Connection Diagram  
Figure 1. Top View  
See Package Number D (R-PDSO-G8), NGK0008A  
Block Diagram  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2001–2013, Texas Instruments Incorporated  
DS90LV001  
SNLS067E JANUARY 2001REVISED APRIL 2013  
www.ti.com  
Absolute Maximum Ratings(1)  
Supply Voltage (VCC  
)
0.3V to +4V  
0.3V to (VCC + 0.3V)  
0.3V to +4V  
0.3V to +4V  
Continuous  
LVCMOS/LVTTL Input Voltage (EN)  
LVDS Receiver Input Voltage (IN+, IN)  
LVDS Driver Output Voltage (OUT+, OUT)  
LVDS Output Short Circuit Current  
Junction Temperature  
+150°C  
Storage Temperature Range  
65°C to +150°C  
+260°C  
Lead Temperature Range Soldering (4 sec.)  
D Package  
726 mW  
Derate D Package  
NGK Package  
5.8 mW/°C above +25°C  
2.44 W  
Maximum Package Power Dissipation at  
25°C  
Derate NGK Package  
(HBM, 1.5kΩ, 100pF)  
(EIAJ, 0Ω, 200pF)  
19.49 mW/°C above +25°C  
2.5kV  
ESD Ratings  
250V  
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply  
that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.  
Recommended Operating Conditions  
Min  
3.0  
0
Typ  
Max  
3.6  
Units  
V
Supply Voltage (VCC  
)
3.3  
Receiver Input Voltage  
VCC  
+85  
V
Operating Free Air Temperature  
40  
+25  
°C  
2
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SNLS067E JANUARY 2001REVISED APRIL 2013  
Electrical Characteristics  
Over recommended operating supply and temperature ranges unless otherwise specified(1)(2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
LVCMOS/LVTTL DC SPECIFICATIONS (EN)  
VIH  
VIL  
IIH  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
Input Clamp Voltage  
2.0  
VCC  
0.8  
V
V
GND  
VIN = 3.6V or 2.0V, VCC = 3.6V  
VIN = GND or 0.8V, VCC = 3.6V  
ICL = 18 mA  
+7  
±1  
+20  
±10  
1.5  
μA  
μA  
V
IIL  
VCL  
0.6  
LVDS OUTPUT DC SPECIFICATIONS (OUT)  
VOD  
Differential Output Voltage  
RL = 100Ω  
Figure 2 and Figure 3  
250  
325  
450  
20  
mV  
mV  
V
ΔVOD  
Change in Magnitude of VOD for Complimentary  
Output States  
VOS  
Offset Voltage  
RL = 100Ω  
Figure 2  
1.080  
1.19  
1.375  
20  
ΔVOS  
Change in Magnitude of VOS for Complimentary  
Output States  
mV  
IOZ  
Output TRI-STATE Current  
EN = 0V, VOUT = VCC or GND  
VCC = 0V, VOUT = 3.6V or GND  
EN = VCC, VOUT+ and VOUT= 0V  
EN = VCC, VOD = 0V  
±1  
±1  
±10  
±10  
24  
12  
μA  
μA  
IOFF  
IOS  
Power-Off Leakage Current  
Output Short Circuit Current(3)  
Differential Output Short Circuit Current(3)  
16  
7  
mA  
mA  
IOSD  
LVDS RECEIVER DC SPECIFICATIONS (IN)  
VTH  
VTL  
VCMR  
IIN  
Differential Input High Threshold  
Differential Input Low Threshold  
Common Mode Voltage Range  
Input Current  
VCM = +0.05V, +1.2V or +3.25V  
VID = 100mV, VCC = 3.3V  
0
0
+100  
mV  
mV  
V
100  
0.05  
3.25  
±10  
±10  
6
VIN = +3.0V  
VIN = 0V  
VCC = 3.6V or 0V  
±1  
±1  
1
μA  
μA  
μA  
μA  
ΔIIN  
Change in Magnitude of IIN  
VIN = +3.0V  
VIN = 0V  
VCC = 3.6V or 0V  
1
6
SUPPLY CURRENT  
ICCD Total Supply Current  
ICCZ TRI-STATE Supply Current  
EN = VCC, RL = 100Ω, CL = 5 pF  
47  
22  
70  
35  
mA  
mA  
EN = 0V  
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground  
except VOD and ΔVOD  
.
(2) All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.  
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.  
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AC Electrical Characteristics  
Over recommended operating supply and temperature ranges unless otherwise specified(1)  
Symbol  
tPHLD  
tPLHD  
tSKD1  
tSKD3  
tSKD4  
tLHT  
Parameter  
Conditions  
Min  
1.0  
1.0  
Typ  
1.4  
1.4  
20  
Max  
Units  
ns  
Differential Propagation Delay High to Low  
RL = 100, CL = 5pF  
Figure 4 and Figure 5  
2.0  
2.0  
200  
60  
Differential Propagation Delay Low to High  
ns  
(2)(3)  
Pulse Skew |tPLHD tPHLD  
Part to Part Skew(2)(4)  
Part to Part Skew(2)(5)  
Rise Time(2)  
|
ps  
0
ps  
400  
450  
450  
25  
ps  
RL = 100, CL = 5pF  
Figure 4 and Figure 6  
200  
200  
320  
310  
3
ps  
tHLT  
Fall Time(2)  
ps  
tPHZ  
Disable Time (Active High to Z)  
RL = 100, CL = 5pF  
ns  
Figure 7 and Figure 8  
tPLZ  
Disable Time (Active Low to Z)  
3
25  
ns  
tPZH  
Enable Time (Z to Active High)  
25  
25  
45  
ns  
tPZL  
Enable Time (Z to Active Low)  
45  
ns  
tDJ  
LVDS Data Jitter, Deterministic (Peak-to-Peak)(6)  
VID = 300mV; PRBS = 223 1 data; VCM  
= 1.2V at 800Mbps (NRZ)  
100  
2.2  
135  
3.5  
ps  
ps  
tRJ  
LVDS Clock Jitter, Random(6)  
VID = 300mV; VCM = 1.2V at 400MHz  
clock  
(1) All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.  
(2) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT (process,  
voltage and temperature) range.  
(3) tSKD1, |tPLHD tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative  
going edge of the same channel.  
(4) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This  
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.  
(5) tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices  
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max Min|  
differential propagation delay.  
(6) The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT range with  
the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A  
(digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ  
1.8ps.  
=
4
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SNLS067E JANUARY 2001REVISED APRIL 2013  
DC Test Circuits  
Figure 2. Differential Driver DC Test Circuit  
Figure 3. Differential Driver Full Load DC Test Circuit  
AC Test Circuits and Timing Diagrams  
Figure 4. LVDS Output Load  
Figure 5. Propagation Delay Low-to-High and High-to-Low  
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Figure 6. LVDS Output Transition Time  
Figure 7. TRI-STATE Delay Test Circuit  
Figure 8. Output active to TRI-STATE and TRI-STATE to active output time  
6
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DS90LV001 Pin Descriptions (SOIC and WSON)  
Pin Name  
Pin #  
Input/Output  
Description  
GND  
IN −  
IN+  
1
2
3
4
5
6
7
8
P
I
Ground  
Inverting receiver LVDS input pin  
Non-inverting receiver LVDS input pin  
No Connect  
I
NC  
VCC  
P
O
O
I
Power Supply, 3.3V ± 0.3V.  
Non-inverting driver LVDS output pin  
Inverting driver LVDS output pin  
OUT+  
OUT -  
EN  
Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRI-  
STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL levels.  
DAP  
NA  
NA  
Die Attach Pad or DAP (WSON Package only). The DAP is NOT connected to the  
device GND nor any other pin. It is still recommended to connect the DAP to a GND  
plane of a PCB for enhenced heat dissipation.  
TYPICAL APPLICATIONS  
Backplane Stub-Hider Application  
Cable Repeater Application  
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APPLICATION INFORMATION  
MODE OF OPERATION  
The DS90LV001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and  
one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and  
the unterminated receivers on the individual cards. Although it is generally recognized that this distance should  
be as short as possible to maximize system performance, real-world packaging concerns and PCB designs often  
make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the WSON  
package, can improve system performance by allowing the receiver to be placed very close to the main  
transmission line either on the backplane itself or very close to the connector on the card. Longer traces to the  
LVDS receiver may be placed after the DS90LV001. This very small WSON package is a 75% space savings  
over the SOIC package.  
INPUT FAILSAFE  
The receiver inputs of the DS90LV001 do not have internal failsafe biasing. For point-to-point and multidrop  
applications with a single source, failsafe biasing may not be required. When the driver is off, the link is in-active.  
If failsafe biasing is required, this can be accomplished with external high value resistors. Using the equations in  
the LVDS Owner"s Manual Chapter 4, the IN+ should be pull to VCC (3.3V) with 20kΩ and the INshould be pull  
to GND with 12kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a  
minimum amount of distortion.  
PCB LAYOUT AND POWER SYSTEM BYPASS  
Circuit board layout and stack-up for the DS90LV001 should be designed to provide noise-free power to the  
device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize  
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by  
using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the  
PCB power system which improves power supply filtering, especially at high frequencies, and makes the value  
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF  
ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum  
capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the  
power supply voltage being used. It is recommended practice to use two vias at each power pin of the  
DS90LV001 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to  
half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass  
components.  
8
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The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding  
and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be  
effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via  
placement also improves signal integrity on signal transmission lines by providing short paths for image currents  
which reduces signal distortion. The planes should be pulled back from all transmission lines and component  
mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric  
separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so  
minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component  
mounting pads.  
There are more common practices which should be followed when designing PCBs for LVDS signaling. Please  
see application note AN-1108 for guidelines. In addition, application note AN-1187 has additional information  
specifically related to WSON recommendations.  
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Typical Performance Curves  
Output High Voltage vs  
Power Supply Voltage  
Output Low Voltage vs  
Power Supply Voltage  
Figure 9.  
Figure 10.  
Output Short Circuit Current vs  
Power Supply Voltage  
Differential Output Short Circuit Current vs  
Power Supply Voltage  
Figure 11.  
Figure 12.  
Output TRI-STATE Current vs  
Power Supply Voltage  
Offset Voltage vs  
Power Supply Voltage  
Figure 13.  
Figure 14.  
10  
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Typical Performance Curves (continued)  
Differential Output Voltage  
vs Power Supply Voltage  
Differential Output Voltage  
vs Load Resistor  
Figure 15.  
Figure 16.  
Power Supply Current  
vs Frequency  
Power Supply Current vs  
Power Supply Voltage  
Figure 17.  
Figure 18.  
TRI-STATE Power Supply Current vs  
Power Supply Voltage  
Differential Transition Voltage vs  
Power Supply Voltage  
Figure 19.  
Figure 20.  
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Typical Performance Curves (continued)  
Differential Propagation Delay vs  
Power Supply Voltage  
Differential Propagation Delay vs  
Ambient Temperature  
Figure 21.  
Figure 22.  
Differential Skew vs  
Power Supply Voltage  
Differential Skew vs  
Ambient Temperature  
Figure 23.  
Figure 24.  
Transition Time vs  
Power Supply Voltage  
Transition Time vs  
Ambient Temperature  
Figure 25.  
Figure 26.  
12  
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Typical Performance Curves (continued)  
Differential Propagation Delay vs  
Differential Input Voltage  
Differential Propagation Delay vs  
Common-Mode Voltage  
Figure 27.  
Figure 28.  
Peak-to-Peak Output Jitter at VCM = 0.4V vs  
Differential Input Voltage  
Peak-to-Peak Output Jitter at VCM = 2.9V vs  
Differential Input Voltage  
Figure 29.  
Figure 30.  
Peak-to-Peak Output Jitter at VCM = 1.2V vs  
Differential Input Voltage  
Peak-to-Peak Output Jitter at VCM = 1.2V vs  
Ambient Temperature  
Figure 31.  
Figure 32.  
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REVISION HISTORY  
Changes from Revision D (April 2013) to Revision E  
Page  
Changed layout of National Data Sheet to TI format .......................................................................................................... 13  
14  
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PACKAGE OPTION ADDENDUM  
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1-Nov-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
1000  
1000  
(1)  
(2)  
(6)  
(3)  
(4/5)  
DS90LV001TLD  
NRND  
ACTIVE  
WSON  
WSON  
NGK  
8
8
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
001  
001  
DS90LV001TLD/NOPB  
NGK  
Green (RoHS  
& no Sb/Br)  
Level-3-260C-168 HR  
DS90LV001TLDX/NOPB  
DS90LV001TM  
ACTIVE  
NRND  
WSON  
SOIC  
SOIC  
SOIC  
SOIC  
NGK  
D
8
8
8
8
8
4500  
95  
Green (RoHS  
& no Sb/Br)  
CU SN  
Call TI  
Level-3-260C-168 HR  
Call TI  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
001  
TBD  
LV001  
TM  
DS90LV001TM/NOPB  
DS90LV001TMX  
ACTIVE  
NRND  
D
95  
Green (RoHS  
& no Sb/Br)  
SN | CU SN  
Call TI  
Level-1-260C-UNLIM  
Call TI  
LV001  
TM  
D
2500  
2500  
TBD  
LV001  
TM  
DS90LV001TMX/NOPB  
ACTIVE  
D
Green (RoHS  
& no Sb/Br)  
SN | CU SN  
Level-1-260C-UNLIM  
LV001  
TM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
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1-Nov-2013  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
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Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Oct-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
DS90LV001TLD  
WSON  
WSON  
NGK  
NGK  
NGK  
D
8
8
8
8
8
1000  
1000  
4500  
2500  
2500  
178.0  
178.0  
330.0  
330.0  
330.0  
12.4  
12.4  
12.4  
12.4  
12.4  
3.3  
3.3  
3.3  
6.5  
6.5  
3.3  
3.3  
3.3  
5.4  
5.4  
1.0  
1.0  
1.0  
2.0  
2.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
DS90LV001TLD/NOPB  
DS90LV001TLDX/NOPB WSON  
DS90LV001TMX  
SOIC  
SOIC  
DS90LV001TMX/NOPB  
D
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Oct-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
DS90LV001TLD  
DS90LV001TLD/NOPB  
DS90LV001TLDX/NOPB  
DS90LV001TMX  
WSON  
WSON  
WSON  
SOIC  
NGK  
NGK  
NGK  
D
8
8
8
8
8
1000  
1000  
4500  
2500  
2500  
210.0  
213.0  
367.0  
367.0  
367.0  
185.0  
191.0  
367.0  
367.0  
367.0  
35.0  
55.0  
35.0  
35.0  
35.0  
DS90LV001TMX/NOPB  
SOIC  
D
Pack Materials-Page 2  
MECHANICAL DATA  
NGK0008A  
LDA08A (Rev C)  
www.ti.com  
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配单直通车
DS90LV001TMX产品参数
型号:DS90LV001TMX
是否Rohs认证: 不符合
生命周期:Transferred
IHS 制造商:NATIONAL SEMICONDUCTOR CORP
包装说明:SOIC-8
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.27
差分输出:YES
驱动器位数:1
高电平输入电流最大值:0.00002 A
输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER
接口标准:EIA-644-A; TIA-644-A
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
长度:4.9 mm
湿度敏感等级:1
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
最小输出摆幅:0.25 V
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):235
电源:3.3 V
认证状态:Not Qualified
最大接收延迟:2 ns
接收器位数:1
座面最大高度:1.75 mm
子类别:Line Driver or Receivers
最大压摆率:70 mA
最大供电电压:3.6 V
最小供电电压:3 V
标称供电电压:3.3 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:30
宽度:3.9 mm
Base Number Matches:1
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