EL7536IY各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

当前位置：IC37首页_>E字母起始型号索引_>E字母起始型号索引第406页更新时间：2024-10-24 08:30:09

产品型号EL7536IY的概述

芯片EL7536IY的详细概述 EL7536IY是一款高性能的视频放大器，广泛应用于视频信号处理、图像处理及相关的消费电子产品中。该芯片具有出色的带宽和低失真特性，能够在多种应用环境下保持信号的高质量传输。芯片EL7536IY的详细参数在讨论EL7536IY之前，有必要详细了解其技术参数。这些参数直接影响芯片的性能和应用效能。EL7536IY的主要参数包括： - 工作电压：EL7536IY的工作电压范围为4.5V至5.5V，是典型的单电源供电设计，满足多种电源配置的需求。 - 带宽：该芯片的带宽通常在100MHz以上，适合高频视频信号的传输。 - 增益：EL7536IY具有可调增益设置，一般提供0dB到20dB之间的增益选择，能够适应不同的输入输出条件。 - 输出电流：输出电流能力最高可达50mA，适应大多数负载情况。 - 输入类型：支持单端输入和差分输入，适合多种信号源连接...

产品型号EL7536IY的Datasheet PDF文件预览

EL7536

Data Sheet

August 10, 2005

FN7396.5

Monolithic 1A Step-Down Regulator

Features

The EL7536 is a synchronous, integrated FET 1A step-down

regulator with internal compensation. It operates with an

input voltage range from 2.5V to 5.5V, which accommodates

supplies of 3.3V, 5V, or a Li-Ion battery source. The output

• Less than 0.15in (0.97cm ) footprint for the complete 1A

converter

• Components on one side of PCB

• Max height 1.1mm MSOP10

can be externally set from 0.8V to V with a resistive

divider.

• 100ms Power-On-Reset output (POR)

• Internally-compensated voltage mode controller

• Up to 94% efficiency

The EL7536 features PWM mode control. The operating

frequency is typically 1.4MHz. Additional features include a

100ms Power-On-Reset output, <1µA shut-down current,

short-circuit protection, and over-temperature protection.

• <1µA shut-down current

• Overcurrent and over-temperature protection

• Pb-Free plus anneal available (RoHS compliant)

The EL7536 is available in the 10-pin MSOP package,

making the entire converter occupy less than 0.15in of PCB

area with components on one side only. Both packages are

specified for operation over the full -40°C to +85°C

temperature range.

Applications

• PDA and pocket PC computers

Ordering Information

• Bar code readers

PART NUMBER

TAPE &

REEL

PKG.

• Cellular phones

(BRAND)

PACKAGE

DWG. #

• Portable test equipment

• Li-Ion battery powered devices

• Small form factor (SFP) modules

EL7536IY

10-Pin MSOP

MDP0043

(BDAAA)

EL7536IY-T7

(BDAAA)

10-Pin MSOP

7”

Pinout and Typical Application Diagram

EL7536IY-T13

(BDAAA)

13”

EL7536

TOP VIEW

EL7536IYZ

(BFAAA) (Note)

10-Pin MSOP

(Pb-free)

EL7536IYZ-T7

(BFAAA) (Note)

10-Pin MSOP

(Pb-free)

7”

R *

100kΩ

EL7536IYZ-T13

(BFAAA) (Note)

10-Pin MSOP

(Pb-free)

13”

SGND

PGND

FB 10

R *

124kΩ

POR

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

10µF

POR

1.8µH

(1.8V@1A)

VIN

(2.5V-6V)

100Ω

VDD

RSI

0.1µF

100kΩ

* V = 0.8V * (1 + R / R )

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

EL7536

Absolute Maximum Ratings (T = 25°C)

, V , POR to SGND. . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +145°C

IN DD

LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V + +0.3V)

RSI, EN, V , FB to SGND. . . . . . . . . . . . . . . -0.3V to (V + +0.3V)

PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: T = T = T

Electrical Specifications

= V = V

= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V = 1.8V, unless otherwise specified.

EN O

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

DC CHARACTERISTICS

Feedback Input Voltage

790

800

810

250

5.5

2.2

2.4

500

Feedback Input Current

Input Voltage

, V

2.5

IN DD

IN,OFF

IN,ON

Minimum Voltage for Shutdown

Maximum Voltage for Startup

Supply Current

falling

rising

2.2

PWM, V = V

IN DD

= 5V

400

0.1

µA

mΩ

EN = 0, V = V

PMOS FET Resistance

NMOS FET Resistance

Current Limit

= 5V, wafer test only

100

DS(ON)-PMOS

DS(ON)-NMOS

LMAX

1.5

145

130

Over-temperature Threshold

Over-temperature Hysteresis

EN, RSI Current

T rising

T falling

°C

OT,OFF

OT,ON

, I

EN RSI

, V

EN RSI

= 0V and 3.3V

-1

0.8

, V

EN1 RSI1

EN, RSI Rising Threshold

EN, RSI Falling Threshold

= 3.3V

rising

2.4

, V

EN2 RSI2

Minimum V for POR, WRT Targeted

POR

Value

falling

POR Voltage Drop

= 5mA

OLPOR

SINK

AC CHARACTERISTICS

PWM Switching Frequency

Minimum RSI Pulse Width

Soft-start Time

1.4

1.5

1.75

MHz

PWM

Guaranteed by design

RSI

650

100

µs

Power On Reset Delay Time

120

POR

FN7396.5

August 10, 2005

EL7536

Pin Descriptions

PIN NUMBER

PIN NAME

PIN FUNCTION

SGND

PGND

Negative supply for the controller stage

Negative supply for the power stage

Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage

VIN

Positive supply for the power stage

Power supply for the controller stage

Resets POR timer

VDD

RSI

Enable

POR

Power on reset open drain output

Output voltage sense

Voltage feedback input; connected to an external resistor divider between V and SGND for variable

output

Block Diagram

10pF

124K

100K

CURRENT

LIMIT

PWM

COMPEN-

SATION

PWM

COMPARATOR

P-DRIVER

1.8µ

CONTROL

LOGIC

RAMP

GENERATOR

CLOCK

1.4MHz

1.8V

SOFT-

START

10µF

N-DRIVER

UNDER-

VOLTAGE

LOCKOUT

–

PGND

POR

BANDGAP

REFERENCE

100K

2.5V-

3.5V

TEMPERATURE

SENSE

SGND

RSI

POR

FN7396.5

August 10, 2005

EL7536

Performance Curves and Waveforms

All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise

noted.

=5V

=3.3V

100

=3.3V

=2.5V

=1.8V

=2.5V

=1V

V =1.8V

=1.2V

200

400

600

(mA)

800

1000

200

400

600

(mA)

800

1000

FIGURE 1. EFFICIENCY

FIGURE 2. EFFICIENCY

0.1%

0.0%

1.44

1.42

1.4

=3.3V I =1A

=5V I =1A

=5V I =0A

-0.1%

=3.3V I =0A

=3.3V

-0.2%

-0.3%

-0.4%

-0.5%

1.38

1.36

1.34

1.32

=5V

0.2

0.4

0.6

0.8

-50

100

150

(A)

(°C)

FIGURE 4. LOAD REGULATIONS

FIGURE 3. F vs JUNCTION TEMPERATURE

0.1%

0.0%

=5V I =0A

=3.3V I =0A

-0.1%

-0.2%

-0.3%

-0.4%

-0.5%

=3.3V I =1A

=5V I =1A

-0.6%

-0.7%

-50

100

150

3.5

4.5

2.5

(°C)

(V)

FIGURE 6. NO LOAD INPUT CURRENT

FIGURE 5. LOAD/LINE REGULATIONS vs JUNCTION

TEMPERATURE

FN7396.5

August 10, 2005

EL7536

Performance Curves and Waveforms (Continued)

All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise

noted.

(2V/d)

(1V/d)

(2V/d)

(0.5A/d)

POR

(2V/d)

(1V/d)

50ms/d

0.5ms/d

FIGURE 8. START-UP 2

FIGURE 7. START-UP 1

(2V/d)

0.75A

0.25A

(2V/d)

RSI

(2V/d)

∆V

20mV/d

POR

(2V/d)

0.2ms/d

50ms/d

FIGURE 9. POR FUNCTION

FIGURE 10. TRANSIENT RESPONSE

∆V

100mV/d

0.5A/d

2V/d

∆V

10mV/d

1µs/d

FIGURE 11. STEADY-STATE

FN7396.5

August 10, 2005

EL7536

Performance Curves and Waveforms (Continued)

All waveforms are taken at V =3.3V, V =1.8V, I =1A with component values shown on page 1 at room ambient temperature, unless otherwise

noted.

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.2

0.7

0.6

0.5

0.4

0.3

0.2

0.1

607mW

1.087W

0.8

0.6

0.4

0.2

75 85 100

125

150

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

and the output capacitor act as a low pass filter, the duty

Applications Information

Product Description

The EL7536 is a synchronous, integrated FET 1A step-down

regulator which operates from an input of 2.5V to 6V. The

output voltage is user-adjustable with a pair of external

resistors.

cycle ratio is approximately equal to V divided by V

The output LC filter has a second order effect. To maintain

the stability of the converter, the overall controller must be

compensated. This is done with the fixed internally

compensated error amplifier and the PWM compensator.

Because the compensations are fixed, the values of input

and output capacitors are 10µF to 22µF ceramic. The

inductor is nominally 1.8µH, but 1.5µA to 2.2µH can be used.

The internally-compensated controller makes it possible to

use only two ceramic capacitors and one inductor to form a

complete, very small footprint 1A DC:DC converter.

100% Duty Ratio Operation

Start-Up and Shut-Down

EL7536 utilizes CMOS power FET's as the internal

synchronous power switches. The upper switch is a PMOS

and lower switch a NMOS. This not only saves a boot

capacitor, it also allows 100% turn-on of the upper PFET

When the EN pin is tied to V , and V reaches

approximately 2.4V, the regulator begins to switch. The

output voltage is gradually increased to ensure proper soft-

start operation.

switch, achieving V close to V . The maximum achievable

is,

When the EN pin is connected to a logic low, the EL7536 is

in the shut-down mode. All the control circuitry and both

= V – (R + R

) × I

DSON1

MOSFETs are off, and V

falls to zero. In this mode, the

OUT

total input current is less than 1µA.

Where RL is the DC resistance on the inductor and R

the PFET on-resistance, nominal 70mΩ at room temperature

with tempco of 0.2mΩ/°C.

DSON1

When the EN reaches logic HI, the regulator repeats the

start-up procedure, including the soft-start function.

As the input voltage drops gradually close or even bellow the

PWM Operation

preset V , the converter gets into 100% duty ratio. At this

In the PWM mode, the P channel MOSFET and N channel

MOSFET always operate complementary. When the

PMOSFET is on and the NMOSFET off, the inductor current

increases linearly. The input energy is transferred to the

output and also stored in the inductor. When the P channel

MOSFET is off and the N channel MOSFET on, the inductor

current decreases linearly, and energy is transferred from

the inductor to the output. Hence, the average current

through the inductor is the output current. Since the inductor

condition, the upper PFET needs some minimum turn-off

time if it is turned off. This off-time is related to input/output

conditions. This makes the duty ratio appears randomly and

increases the output ripple somewhat until the 100% duty

ratio is reached. Larger output capacitor could reduce the

random-looking ripple. Users need to verify if this condition

has adverse effect on overall circuit if close to 100% duty

ratio is expected.

FN7396.5

August 10, 2005

EL7536

RSI/POR Function

(V - V ) × V

∆I = --------------------------------------------

When powering up, the open-collector Power-On-Reset

L × V × f

output holds low for about 100ms after V reaches the

• L is the inductance

• f the switching frequency (nominally 1.4MHz)

preset voltage. When the active-HI reset signal RSI is

issued, POR goes to low immediately and holds for the

same period of time after RSI comes back to LOW. The

output voltage is unaffected. (Please refer to the timing

diagram). When the function is not used, connect RSI to

The inductor must be able to handle I for the RMS load

current, and to assure that the inductor is reliable, it must

handle the 1.5A surge current that can occur during a

current limit condition.

ground and leave open the pull-up resister R at POR pin.

The POR output also serves as a 100ms delayed Power

Current Limit and Short-Circuit Protection

Good signal when the pull-up resister R is installed. The

The current limit is set at about 1.5A for the PMOS. When a

short-circuit occurs in the load, the preset current limit

restricts the amount of current available to the output, which

causes the output voltage to drop below the preset voltage.

In the meantime, the excessive current heats up the

regulator until it reaches the thermal shut-down point.

RSI pin needs to be directly (or indirectly through a resister

R ) connected to Ground for this to function properly.

MIN

25ns

Thermal Shut-Down

RSI

Once the junction reaches about 145°C, the regulator shuts

down. Both the P channel and the N channel MOSFETs turn

off. The output voltage will drop to zero. With the output

MOSFETs turned off, the regulator will soon cool down.

Once the junction temperature drops to about 130°C, the

regulator will restart again in the same manner as EN pin

connects to logic HI.

100ms

POR

FIGURE 14. RSI & POR TIMING DIAGRAM

Output Voltage Selection

Users can set the output voltage of the converter with a

resister divider, which can be chosen based on the following

formula:

Thermal Performance

The EL7536 is in a fused-lead MSOP10 package. Compared

with regular MSOP10 package, the fused-lead package









provides lower thermal resistance. The θ is 100°C/W on a

= 0.8 × 1 + ------





4-layer board and 125°C/W on 2-layer board. Maximizing the

copper area around the pins will further improve the thermal

performance.

Component Selection

Because of the fixed internal compensation, the component

choice is relatively narrow. We recommend 10µF to 22µF

multi-layer ceramic capacitors with X5R or X7R rating for

both the input and output capacitors, and 1.5µH to 2.2µH

inductance for the inductor.

Layout Considerations

The layout is very important for the converter to function

properly. The following PC layout guidelines should be

followed:

• Separate the Power Ground ( ) and Signal Ground ( );

connect them only at one point right at the pins

At extreme conditions (V < 3V, I > 0.7A, and junction

temperature higher than 75°C), input cap C is

• Place the input capacitor as close to V and PGND pins

recommended to be 22µF. Otherwise, if any of the above 3

as possible

conditions is not true, C can remain as low as 10µF.

• Make the following PC traces as small as possible:

The RMS current present at the input capacitor is decided by

the following formula:

- from L pin to L

- from C to PGND

× (V - V

)

-----------------------------------------------

× I

• If used, connect the trace from the FB pin to R1 and R2 as

close as possible

INRMS

This is about half of the output current I for all the V . This

• Maximize the copper area around the PGND pin

input capacitor must be able to handle this current.

• Place several via holes under the chip to additional ground

plane to improve heat dissipation

The inductor peak-to-peak ripple current is given as:

The demo board is a good example of layout based on this

outline. Please refer to the EL7536 Application Brief.

FN7396.5

August 10, 2005

EL7536

MSOP Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at

<http://www.intersil.com/design/packages/index.asp>

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7396.5

August 10, 2005

EL7536IY相关文章

配单直通车

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

EL7536IY产品参数

型号:	EL7536IY
Brand Name：	Intersil
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	INTERSIL CORP
零件包装代码：	MSOP
包装说明：	TSSOP, TSSOP10,.19,20
针数：	10
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	5.23
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	5.5 V
最小输入电压：	2.5 V
标称输入电压：	3.3 V
JESD-30 代码：	S-PDSO-G10
JESD-609代码：	e0
长度：	3 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	10
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	1.2 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP10,.19,20
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	1750 kHz
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm

电子百科

产品导航

产品型号EL7536IY的概述

产品型号EL7536IY的Datasheet PDF文件预览

EL7536IY相关产品

EL7536IY相关文章

IC37:专业IC行业平台