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产品型号FIN3386MTDX的概述

芯片概述 FIN3386MTDX是一款由Fairchild Semiconductor（现为ON Semiconductor）推出的高性能电源管理IC。该芯片广泛应用于开关电源、LED驱动、DC-DC转换及其他需要高效功率管理的电子系统中。其设计理念在于实现高效率、低功耗和高稳定性的电源输出，并支持多种工作模式，实现不同负载条件下的最优性能。此芯片通常采用小型封装，便于集成到各种电路板设计中，尤其适合需要节省空间并提高散热效率的应用场景。FIN3386MTDX凭借其创新的设计和卓越的性能，已经成为工程师和设计师的热门选择。芯片详细参数 FIN3386MTDX的主要技术参数如下： 1. 输入电压范围: 2.5V至30V 2. 输出电压: 可调，支持多种输出电压配置 3. 输出电流: 最大可达2A 4. 工作频率: 典型为100kHz至1MHz 5. 效率: 高达95% 6. 温度范围...

产品型号FIN3386MTDX的Datasheet PDF文件预览

March 2012

FIN3385 / FIN3386

Low-Voltage, 28-Bit, Flat-Panel Display Link

Serializer / Deserializer

Features

Description

The FIN3385 and FIN3386 transform 28-bit wide parallel

Low-Voltage TTL (LVTTL) data into four serial Low

Voltage Differential Signaling (LVDS) data streams. A

phase-locked transmit clock is transmitted in parallel

with the data stream over a separate LVDS link. Every

cycle of transmit clock, 28-bits of input LVTTL data are

sampled and transmitted.

Operation -40°C to +85°C

Low Power Consumption

20MHz to 85MHz Shift Clock Support

±1V Common-Mode Range around 1.2V

Narrow Bus Reduces Cable Size and Cost

High Throughput (up to 2.38Gbps)

Internal PLL with No External Component

Compatible with TIA/EIA-644 Specification

56-Lead, TSSOP Package

The FIN3386 receives and converts the 4/3 serial LVDS

data streams back into 28/21 bits of LVTTL data, acting

as the deserializer.

For the FIN3385, at a transmit clock frequency of

85MHz, 28-bits of LVTTL data are transmitted at a rate

of 595Mbps per LVDS channel.

This pair solves EMI and cable size problems

associated with wide and high-speed TTL interfaces.

Ordering Information

Operating

Temperature Range

Packing

Part Number

Package

Method

FIN3385MTDX

FIN3386MTDX

56-Lead Thin-Shrink Small-Outline Package

Tape and Reel

-40 to +85°C

(TSSOP), JEDEC MO-153,6.1mm Wide

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Block Diagrams

Figure 1. FIN3385 Transmitter Functional Diagram

Figure 2. FIN3386 Receiver Functional Diagram

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Transmitter Pin Configuration

Figure 3. FIN3385 (28:4 Transmitter) Pin Assignments

Pin Definitions

Pin Names

TxIn

I/O Types

Number of Pins

Description of Signals

28/21

LVTTL Level Input

TxCLKIn

TxOut+

LVTTL Level Clock Input, the rising edge is for data strobe

Positive LVDS Differential Data Output

4/3

TxOut-

Negative LVDS Differential Data Output

Positive LVDS Differential Clock Output

Negative LVDS Differential Clock Output

TxCLKOut+

TxCLKOut-

Rising Edge Data Strobe: Assert HIGH (V_CC

Falling Edge Data Strobe: Assert LOW (Ground)

)

R_FB

LVTTL Level Power-Down Input Assertion (LOW) puts the

outputs in High-Impedance state

/PwrDn

PLL VCC

PLL GND

LVDS V_CC

LVDS GND

V_CC

Power Supply Pin for PLL

Ground Pins for PLL

Power Supply Pin for LVDS Output

Ground Pins for LVDS Output

Power Supply Pins for LVTTL Input

Ground Pin for LVTTL Input

GND

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Receiver Pin Configuration

Figure 4. FIN3386 (28:4 Receiver) Pin Assignments

Pin Definitions

Pin Names

RxIn

I/O Types

Number of Pins

Description of Signals

Negative LVDS Differential Data Output

Positive LVDS Differential Data Output

Negative LVDS Differential Data Input

Positive LVDS Differential Clock Input

LVTTL Level Data Output, goes HIGH for /PwrDn LOW

LVTTL Clock Output

4/3

RxIn+

4/3

RxCLKIn-

RxCLKIn+

RxOut

28/21

RxCLKOut-

/PwrDn

LVTTL Level Input. Refer to Table 2

Power Supply Pin for PLL

PLL VCC

PLL GND

LVDS V_CC

LVDS GND

V_CC

Ground Pins for PLL

Power Supply Pin for LVDS Input

Ground Pins for LVDS Input

Power Supply for LVTTL Output

Ground Pins for LVTTL Output

GND

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Truth Tables

Table 1. Input / Output Truth Table

Inputs

Outputs

TxIn

Active

TxCLKIn

/PwrDn⁽¹⁾

HIGH

LOW

TxOut±

LOW / HIGH

LOW

TxCLKOut±

LOW / HIGH

Don’t Care⁽²⁾

LOW / HIGH

Don’t Care⁽²⁾

High Impedance

Active

LOW / HIGH / High Impedance

Active

Floating

Don’t Care

Floating

LOW

Don’t Care

High Impedance

Notes:

1. The outputs of the transmitter or receiver remain in a high-impedance state until V_CCreaches 2V.

2. TxCLKOut± settles at a free-running frequency when the part is powered up, /PwrDn is HIGH, and the TxCLKIn

is a steady logic level (LOW / HIGH / High-Impedance).

Power-Up / Power-Down Operation Truth Tables

The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. Table 2 shows

the operation of the transmitter during power-up and power-down and operation of the /PwrDn pin.

Table 2. Transmitter Power-Up / Power-Down Operation Truth Table

PwrDn

>2V

Normal

>2V

V_CC

TxIN

<2V

Don’t Care

High Impedance

Don’t Care

High Impedance

LOW

Don’t Care

High Impedance

Don’t Care

High Impedance

LOW

Active

HIGH

TxOUT

TxCLKIn

TxCLKOut±

/PwrDn

Table 3. Receiver Power-Up / Power-Down Operation Truth Table

/PwrDn

RxIn±

Don’t Care

Active

LOW/HIGH

Active

Last Valid State

Note 3

HIGH

Note 3

High

Impedance

Last Valid

State

RxOut

LOW

RxCLKIn±

RxCLKOut

Don’t Care

Note 4

Note 3

Note 4

Note 3

High

Impedance

Active

Note 4

/PwrDn

V_CC

LOW

<2V

LOW

<2V

HIGH

<2V

HIGH

<2V

HIGH

<2V

HIGH

<2V

Notes:

3. If the input is terminated and un-driven (high-impedance) or shorted or open (fail-safe condition).

4. For /PwrDn or fail-safe condition, the RxCLKOut pin goes LOW for panel link devices and HIGH for channel link

devices.

5. Shorted means (± inputs are shorted to each other, or ± inputs are shorted to each other and ground or V_CC, or

either ± inputs are shorted to ground or V_CC) with no other current/voltage sources (noise) applied. If the V_IDis still

in the valid range (greater than 100mV) and V_CMis in the valid range (0V to 2.4V), the input signal is still

recognized and the part responds normally.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

-0.3

-0.5

-0.3

Max.

+4.6

Unit

V_CC

Power Supply Voltage

V_{ID_TTL}TTL/CMOS Input/Output Voltage

V_{IO_LVDS}LVDS Input/Output Voltage

I_OSD

T_STG

T_J

LVDS Output Short-Circuit Current

Storage Temperature Range

Continuous

-65

+150

+260

>10.0

>6.5

°C

Maximum Junction Temperature

Lead Temperature, Soldering, 4 Seconds

T_L

I/O to GND

All Pins

Human Body Model, JESD22-A114 (1.5k,100pF)

Machine Model, JESD22-A115 (0, 200pF)

ESD

>400

Note:

6. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life

impaired. The datasheet specifications should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading variables.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_CC

Parameter

Min.

3.0

Max.

3.6

Unit

Supply Voltage

T_A

Operating Temperature

-40

+85

100

°C

V_CCNPPMaximum Supply Noise Voltage⁽⁷⁾

mV_PP

Note:

7. 100mV V_CCnoise should be tested for frequency at least up to 2MHz. All the specifications should be met under

such noise.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Transmitter DC Electrical Characteristics

Typical values are at T_A=25°C and with V_CC=3.3V; minimum and maximum are at over supply voltages and operating

temperatures ranges, unless otherwise specified.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Transmitter LVTTL Input Characteristics

V_IH

V_IL

V_IK

Input HIGH Voltage

Input LOW Voltage

Input Clamp Voltage

2.0

V_CC

0.8

GND

I_IK=-18mA

-0.79

1.8

-1.50

10.0

V_IN=0.4V to 4.6V

V_IN=GND

I_IN

Input Current

µA

-10

Transmitter LVDS Output Characteristics⁽⁸⁾

V_OD

V_OD

V_OS

V_OS

I_OS

Output Differential Voltage

250

450

V_ODMagnitude Change from Differential

LOW-to-HIGH

R_L=100, Figure 5

Offset Voltage

1.125

1.250

1.375

Offset Magnitude Change from

Differential LOW-to-HIGH

µA

Short-Circuit Output Current

V_OUT=0V

-3.5

±1

-5.0

±10

DO=0V to 4.6V,

/PwrDn=0V

I_OZ

Disabled Output Leakage Current

Transmitter Supply Current

32.5MHz

31.0

32.0

37.0

42.0

10.0

29.0

30.0

35.0

39.0

49.5

55.0

60.5

66.0

55.0

41.8

44.0

49.5

55.0

40MHz

66MHz

85MHz

28:4 Transmitter Power Supply Current

for Worst-Case Pattern (with Load)⁽⁹⁾

R_L=100

I_CCWT

µA

Figure 8

I_CCPDTPowered-Down Supply Current

/PwrDn=0.8V

Figure 23⁽¹⁰⁾

32.5MHz

40MHz

66MHz

85MHz

28:4 Transmitter Supply Current for

I_CCGT

16 Grayscale⁽⁹⁾

Notes:

8. Positive current values refer to the current flowing into device and negative values refer to current flowing out of

pins. Voltages are referenced to ground unless otherwise specified (except V_ODand V_OD).

9. The power supply current for both transmitter and receiver can vary with the number of active I/O channels.

10. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test

pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Transmitter AC Electrical Characteristics

Typical values are at T_A=25°C and with V_CC=3.3V; minimum and maximum are at over supply voltages and operating

temperatures ranges, unless otherwise specified.

Symbol

t_TCP

Parameter

Condition

Min.

11.76

0.35

Typ.

Max.

50.00

0.65

Unit

Transmit Clock Period

t_TCH

Transmit Clock (TxCLKIn) HIGH Time

Transmit Clock LOW Time

Figure 9

0.50

t_TCL

0.35

0.65

(10% to 90%)

Figure 10

t_CLKT

TxCLKIn Transition Time (Rising and Falling)

1.0

1.5

6.0

t_JIT

t_XIT

TxCLKIn Cycle-to-Cycle Jitter

TxIn Transition Time

3.0

6.0

LVDS Transmitter Timing Characteristics

t_TLH

t_THL

Differential Output Rise Time (20% to 80%)

Differential Output Fall Time (20% to 80%)

TxIn Setup to TxCLNIn

0.75

1.50

Figure 8

t_STC

t_HTC

t_TPDD

2.5

Figure 9

f=85MHz

TxIn Holds to TxCLNIn

Transmitter Power-Down Delay

Figure 14 ⁽¹¹⁾

100

6.8

(T_A=25°C and

with V_CC=3.3V)

Figure 13

t_TCCD

Transmitter Clock Input to Clock Output Delay

2.8

5.5

Transmitter Output Data Jitter (f=40MHz)⁽¹²⁾

t_TPPB0

t_TPPB1

t_TPPB2

t_TPPB3

t_TPPB4

t_TPPB5

t_TPPB6

Transmitter Output Pulse Position of Bit 0

Transmitter Output Pulse Position of Bit 1

Transmitter Output Pulse Position of Bit 2

Transmitter Output Pulse Position of Bit 3

Transmitter Output Pulse Position of Bit 4

Transmitter Output Pulse Position of Bit 5

Transmitter Output Pulse Position of Bit 6

-0.25

0.25

a-0.25

a+0.25

2a-0.25

3a-0.25

4a-0.25

5a-0.25

6a-0.25

2a+0.25

3a+0.25

4a+0.25

5a+0.25

6a+0.25

Figure 20

a 

f 7

Transmitter Output Data Jitter (f=65MHz) ⁽¹²⁾

t_TPPB0

t_TPPB1

t_TPPB2

t_TPPB3

t_TPPB4

t_TPPB5

t_TPPB6

Transmitter Output Pulse Position of Bit 0

Transmitter Output Pulse Position of Bit 1

Transmitter Output Pulse Position of Bit 2

Transmitter Output Pulse Position of Bit 3

Transmitter Output Pulse Position of Bit 4

Transmitter Output Pulse Position of Bit 5

Transmitter Output Pulse Position of Bit 6

-0.2

0.2

a-0.2

a+0.2

2a-0.2

3a-0.2

4a-0.2

5a-0.2

6a-0.2

2a+0.2

3a+0.2

4a+0.2

5a+0.2

6a+0.2

Figure 20

a 

f  7

Continued on the following page…

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Transmitter AC Electrical Characteristics (Continued)

Over supply voltage and operating temperature ranges, unless otherwise specified.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Transmitter Output Data Jitter (f=85MHz)⁽¹²⁾

t_TPPB0

t_TPPB1

t_TPPB2

t_TPPB3

t_TPPB4

t_TPPB5

t_TPPB6

Transmitter Output Pulse Position of Bit 0

Transmitter Output Pulse Position of Bit 1

Transmitter Output Pulse Position of Bit 2

Transmitter Output Pulse Position of Bit 3

Transmitter Output Pulse Position of Bit 4

Transmitter Output Pulse Position of Bit 5

Transmitter Output Pulse Position of Bit 6

-0.2

0.2

a+0.2

2a+0.2

3a+0.2

4a+0.2

5a+0.2

6a+0.2

370

a-0.2

2a-0.2

3a-0.2

4a-0.2

5a-0.2

6a-0.2

350

210

110

Figure 20

a 

f  7

f=40MHz

f=65MHz

f=85MHz

Figure 26⁽¹²⁾

FIN3385 Transmitter Clock Out Jitter,

Cycle-to-Cycle, Figure 20

t_JCC

230

150

t_TPLLS

Transmitter Phase Lock Loop Set Time⁽¹³⁾

Notes:

11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms

after V_CCreaches 3.0V and /PwrDn pin is above 1.5V.

12. This output data pulse position works for both transmitters for TTL inputs, except the LVDS output bit mapping

difference (see Figure 18). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle

delay is guaranteed when the MSB is output from transmitter.

13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter

of less than 2ns.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Receiver DC Characteristics

Typical values are at T_A=25°C and with V_CC=3.3V. Minimum and maximum values are over supply voltage and

operating temperature ranges unless otherwise specified. Positive current values refer to the current flowing into

device and negative values refer to current flowing out of pins. Voltages are referenced to ground unless otherwise

specified (except V_ODand V_OD).

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

LVTTL/CMOS DC Characteristics

V_IH

V_IL

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Clamp Voltage

Input Current

2.0

GND

2.7

V_CC

0.8

V_OH

V_OL

V_IK

I_IN

I_OH=-0.4mA

I_OL=2mA

3.3

0.06

-0.79

0.30

-1.50

I_IK=-18mA

V_IN=0V to 4.6V

-10

A

Input/Output Power-Off

Leakage Current

V_CC=0V, All LVTTL Inputs / Outputs

0V to 4.6V

I_OFF

I_OS

±10

A

Output Short-Circuit Current

V_OUT=0V

-60

-120

m

Receiver LVDS Input Characteristics

Differential Input Threshold

HIGH

V_TH

Figure 6, Table 4

100

Differential Input Threshold

LOW

V_TL

-100

0.05

V_ICM

I_IN

Input Common Mode Range

Figure 6, Table 4

2.35

±10

V_IN=2.4V, V_CC=3.6V or 0V

V_IN=0V, V_CC=3.6V or 0V

Input Current

A

Receiver Supply Current

4:28 Receiver Power Supply

32.5MHz

40.0MHz

66.0MHz

Current for Worst-Case Pattern

with Load⁽¹⁴⁾

114

135

85.0MHz

I_CCWR

C_L=8pF, Figure 7

3:21 Receiver Power Supply

Current for Worst-Case Pattern

with Load⁽¹⁴⁾

32.5MHz

40.0MHz

66.0MHz

85.0MHz

100

115

I_CCPDTPowered-Down Supply Current /PwrDn=0.8V (RxOut Stays LOW)

A

www.fairchildsemi.com

FIN3385 / FIN3386 • Rev. 1.0.6

Receiver AC Characteristics

Typical values are at T_A=25°C and with V_CC=3.3V; minimum and maximum are at over supply voltages and operating

temperatures ranges, unless otherwise specified.

Symbol

t_RCOP

t_RCOL

Parameter

Receiver Clock Output (RxCLKOut) Period

RxCLKOut LOW Time

Condition

Min.

11.76

4.0

Typ.

Max. Unit

50.00

5.0

6.0

6.5

Figure 12

Rising Edge Strobe

f=85MHz

t_RCOH

t_RSRC

t_RHRC

t_ROLH

RxCLKOut HIGH Time

4.5

RxOut Valid Prior to RxCLKOut

RxOut Valid After RxCLKOut

Output Rise Time (20% to 80%)

Output Fall Time (80% to 20%)

3.5

2.0

1.8

3.5

C_L=8pF, Figure 8

t_ROHL

Receiver Clock Input to Clock Output

Delay⁽¹⁵⁾

T_A=25°C, V_CC=3.3V,

Figure 24

t_RCCD

3.5

5.0

7.5

t_RPPD

Receiver Power-Down Delay

Figure 17

1.0

1.19

2.87

4.55

6.23

7.91

9.59

11.27

µs

t_RSPB0Receiver Input Strobe Position of Bit 0

t_RSPB1Receiver Input Strobe Position of Bit 1

t_RSPB2Receiver Input Strobe Position of Bit 2

t_RSPB3Receiver Input Strobe Position of Bit 3

t_RSPB4Receiver Input Strobe Position of Bit 4

t_RSPB5Receiver Input Strobe Position of Bit 5

t_RSPB6Receiver Input Strobe Position of Bit 6

0.49

2.17

3.85

5.53

7.21

8.89

10.57

290

0.84

2.52

4.20

5.88

7.56

9.24

10.92

Figure 21

f=85MHz

t_RSKM

t_RPLLS

t_RCOP

t_RCOL

t_RCOH

t_RSRC

t_RHRC

t_RCOL

t_RCOH

t_RSRC

t_RHRC

t_ROLH

t_ROHL

RxIN Skew Margin⁽¹⁶⁾

Figure 21

Figure 12

Receiver Phase Lock Loop Set Time

Receiver Clock Output (RxCLKOut) Period

RxCLKOut LOW Time

10.0

6.5

11.0

12.2

11.6

6.3

7.6

7.3

6.3

2.0

1.8

Figure 12

Rising Edge Strobe

f=40MHz

RxCLKOut HIGH Time

RxOUT Valid Prior to RxCLKOut

RxOUT Valid After RxCLKOut

RxCLKOut LOW Time

6.0

5.0

9.0

Figure 12,

RxCLKOut HIGH Time

5.0

4.5

Rising Edge Strobe⁽¹⁷⁾

f=66MHz

RxOUT Valid Prior to RxCLKOut

RxOUT Valid After RxCLKOut

Output Rise Time (20% to 80%)

Output Fall Time (20% to 80%)

4.0

5.0

C_L=8pF⁽¹⁷⁾, Figure 12

Receiver Clock Input to Clock Output

Delay⁽¹⁸⁾

Figure 14, T_A=25°C

and V_CC=3.3v

t_RCCD

3.5

5.0

7.5

µs

t_RPDD

Receiver Power-Down Delay

Figure 17

1.0

t_RSPB0Receiver Input Strobe Position of Bit 0

t_RSPB1Receiver Input Strobe Position of Bit 1

t_RSPB2Receiver Input Strobe Position of Bit 2

t_RSPB3Receiver Input Strobe Position of Bit 3

t_RSPB4Receiver Input Strobe Position of Bit 4

t_RSPB5Receiver Input Strobe Position of Bit 5

t_RSPB6Receiver Input Strobe Position of Bit 6

1.00

4.50

8.10

11.6

15.1

18.8

22.5

1.40

5.00

8.50

11.9

15.6

19.2

22.9

2.15

5.80

9.15

12.6

16.3

19.9

23.6

Figure 21, f=40MHz

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Receiver AC Characteristics

Typical values are at T_A=25°C and with V_CC=3.3V; minimum and maximum are at over supply voltages and operating

temperatures ranges, unless otherwise specified.

Symbol

Parameter

Condition

Min.

0.7

Typ.

1.1

Max. Unit

t_RSPB0Receiver Input Strobe Position of Bit 0

t_RSPB1Receiver Input Strobe Position of Bit 1

t_RSPB2Receiver Input Strobe Position of Bit 2

t_RSPB3Receiver Input Strobe Position of Bit 3

t_RSPB4Receiver Input Strobe Position of Bit 4

t_RSPB5Receiver Input Strobe Position of Bit 5

t_RSPB6Receiver Input Strobe Position of Bit 6

1.4

3.6

5.8

2.9

3.3

5.1

5.5

Figure 21, f=66MHz

7.3

7.7

8.0

9.5

9.9

10.2

12.4

14.6

11.7

13.9

490

400

12.1

14.3

f=40MHz, Figure 21

f=66MHz, Figure 21

Figure 15

t_RSKM

RxIn Skew Margin⁽¹⁹⁾

t_RPLLS

Receiver Phase Lock Loop Set Time

10.0

Notes:

14. The power supply current for the receiver can vary with the number of I/O channels.

15. Total channel latency from serializer to deserializer is (t + t_TCCD) where t is a clock period.

16. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and

minimum/maximum bit position.

17. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with

rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold

time t_RHRC, the clock reference point is the time when falling edge passes through +0.8V.

18. Total channel latency from serializer to deserializer is (t + t_CCD) (2•t + t_RCCD) where t is the clock period.

19. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and

minimum / maximum bit position.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Test Circuits

Figure 5. Differential LVDS Output DC Test Circuit

Notes:

A: For all input pulses, t_Ror t_F<=1ns.

B: C_Lincludes all probe and jig capacitance.

Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit

Table 4. Receiver Minimum and Maximum Input Threshold Test Voltages

Resulting Differential

Input Voltage (mV)

Resulting Common

Mode Input Voltage (V)

Applied Voltages (V)

V_IA

1.25

1.15

2.40

2.30

0.10

V_IB

1.15

1.25

2.30

2.40

V_ID

100

-100

100

-100

100

-100

600

-600

600

-600

600

-600

V_ICM

1.20

2.35

0.05

1.20

2.10

0.30

0.10

0.90

1.50

1.80

2.40

1.50

0.90

2.40

1.80

0.60

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

AC Loadings and Waveforms

Figure 7. Worst-Case Test Pattern

Note:

20. The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and LVTTL/CMOS I/O.

Depending on the valid strobe edge of the transmitter, the TxCLKIn can be rising or falling edge data strobe.

Figure 8. Transmitter LVDS Output Load and Transition Times

Figure 9. Transmitter Setup/Hold and HIGH/LOW Times (Rising-Edge Strobe)

Figure 10. Transmitter Input Clock Transition Time

Figure 11. Transmitter Outputs Channel-to-Channel Skew

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

AC Loadings and Waveforms (Continued)

Figure 12. Receiver Setup/Hold and HIGH/LOW Times

Note:

21. For the receiver with falling-edge strobe, the definition of setup/hold time is slightly different from the one with

rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold

time t_RHRC, the clock reference point is the time when falling edge passes through +0.8V.

Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising-Edge Strobe)

Figure 14. Receiver Clock-In to Clock-Out Delay (Falling-Edge Strobe)

Figure 15. Receiver Phase-Lock-Loop Set Time

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

AC Loadings and Waveforms (Continued)

Figure 16. Transmitter Power-Down Delay

Figure 17. Receiver Power-Down Delay

Figure 18. 28 Parallel LVTTL Inputs Mapped to Four Serial LVDS Outputs

Note:

22. The information in this diagram shows the difference between clock out and the first data bit. A 2-bit cycle delay

is guaranteed when the MSB is output from the transmitter.

Figure 19. 21 Parallel LVTTL Inputs Mapped to Three Serial Outputs

Note:

23. This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit

mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

AC Loadings and Waveforms (Continued)

Figure 20.Transmitter Output Pulse Bit Position

Figure 21.Receiver Input Bit Position

Figure 22. Receiver LVDS Input Skew Margin

Note:

24. t_RSKMis the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).

The minimum and maximum pulse position values are based on the bit position of each of the seven bits within

the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

AC Loadings and Waveforms (Continued)

Figure 23. Transmitter Clock Out Jitter Measurement Setup

Note:

25. Test setup considers no requirement for separation of RMS and deterministic jitter. Other hardware setups,

such as Wavecrest boxes, can be used if no M1 software is available, but the test methodology in Figure 24

should be followed.

Figure 24. Timing Diagram of Transmitter Clock Input with Jitter

Note:

26. This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with

worst jitter ±3ns (cycle-to-cycle) clock input. The specific test methodology is as follows:

27. Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to the right +3ns

when data is HIGH.

28. The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two

clock sources to simulate the worst-case of clock-edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter

at TxCLKOut pin should be measured cross V_CCrange with 100mV noise (V_CCnoise frequency <2MHz).

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

AC Loadings and Waveforms (Continued)

Figure 25. “16-Grayscale” Test Pattern

Note:

29. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test

pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.

Figure 26. Transmitter Phase-Lock-Loop Time

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

Physical Dimensions

8.10

4.05

0.2

C B A

0.30

0.50

0.1 C

-C-

0.50

0.10

0.25

MTD56REV3

Figure 27. 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

FIN3385 / FIN3386 • Rev. 1.0.6

www.fairchildsemi.com

FIN3386MTDX相关文章

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FIN3386MTDX产品参数

型号:	FIN3386MTDX
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	TSSOP
包装说明：	6.10 MM, ROHS COMPLIANT, MO-153EE, TSSOP-56
针数：	56
Reach Compliance Code：	unknown
风险等级：	5.49
差分输出：	NO
输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER
接口标准：	EIA-644; TIA-644
JESD-30 代码：	R-PDSO-G56
JESD-609代码：	e4
长度：	14 mm
湿度敏感等级：	2
功能数量：	4
端子数量：	56
最高工作温度：	70 °C
最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
接收器位数：	4
座面最大高度：	1.1 mm
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
温度等级：	COMMERCIAL
端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	6.1 mm
Base Number Matches：	1

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