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产品型号GTLP16612的概述

芯片GTLP16612的概述 GTLP16612是一款高性能的双向总线收发器，主要用于支持高速数据传输的应用场景。它基于低电压差分信号技术（GTLP），能够有效地进行数据的发送和接收。GTLP16612专为高频通信而设计，广泛应用于计算机、通信设备以及其他电子产品中。由于它的高速度、低功耗和可靠性，GTLP16612成为许多设计工程师首选的解决方案。芯片GTLP16612的详细参数 GTLP16612的主要技术规格包括： - 工作电压范围：3.0V到3.6V。 - 传输速率：支持高达2.5Gbps的信号传输速率。 - 输入和输出电流：每个引脚的输入和输出电流最大为±8mA。 - 环境温度范围：标准操作温度为-40°C到+85°C。 - 引脚数量：28引脚封装（TQFP和BGA均有提供）。 - 引脚排列：支持标准的SOIC、TSSOP和QFN等多种封装形式。在数据传输方面，GTLP1...

产品型号GTLP16612的Datasheet PDF文件预览

March 1995

Revised October 1998

GTLP16612

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description

Features

The GTLP16612 is an 18-bit universal bus transceiver

which provides TTL to GTLP signal level translation. The

device is designed to provide a high speed interface

between cards operating at TTL logic levels and a back-

plane operating at GTLP logic levels. High speed back-

plane operation is a direct result of GTLP’s reduced output

swing (<1V), reduced input threshold levels and output

edge rate control which minimizes signal settling times.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

■ Bidirectional interface between GTLP and TTL logic

levels

■ Designed with Edge Rate Control Circuit to reduce

output noise

■ V_REFpin provides external supply reference voltage for

receiver threshold

■ Submicron Core CMOS technology for low power

dissipation

■ Special PVT Compensation circuitry to provide consis-

tent performance over variations of process, supply

voltage and temperature

Fairchild’s GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different driver

output levels and receiver threshold. GTLP output low volt-

age is typically less than 0.5V, the output high is 1.5V and

the receiver threshold is 1.0V.

■ 5V tolerant inputs and outputs on A-Port

■ Bus-Hold data inputs on A-Port to eliminate the need for

external pull-up resistors for unused inputs

■ Power up/down high impedance

■ TTL compatible Driver and Control inputs

■ A-Port outputs source/sink −32 mA/+32 mA

■ Flow-through architecture optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

Ordering Code:

Order Number

GTLP16612MEA

GTLP16612MTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

DS012390.prf

www.fairchildsemi.com

Pin Descriptions

Connection Diagram

Description

Names

OEAB

OEBA

CEAB

CEBA

LEAB

LEBA

CLKAB

CLKBA

V_REF

A-to-B Output Enable (Active LOW)

B-to-A Output Enable (Active LOW)

A-to-B Clock Enable (Active LOW)

B-to-A Clock Enable (Active LOW)

A-to-B Latch Enable (Transparent HIGH)

B-to-A Latch Enable (Transparent HIGH)

A-to-B Clock Pulse

B-to-A Clock Pulse

GTLP Input Reference Voltage

A1–A18 A-to-B TTL Data Inputs or

B-to-A 3-STATE Outputs

B1–B18 B-to-A GTLP Data Inputs or

A-to-B Open Drain Outputs

Functional Description

The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins

operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches

and D-type flip-flops to allow data flow in transparent, latched and clock mode.

The functional operation is described in the truth table below.

Truth Table

(Note 1)

Inputs

LEAB

Output

Mode

CEAB

OEAB

CLKAB

Latched

storage

B₀(Note 2)

B₀(Note 3)

of A data

Transparent

↑

Clocked storage

of A data

↑

B₀(Note 3)

Clock inhibit

Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.

Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low.

Note 3: Output level before the indicated steady-state input conditions were established.

www.fairchildsemi.com

Logic Diagram

www.fairchildsemi.com

Absolute Maximum Ratings(Note 4)

Recommended Operating

Conditions ^{(Note 6)}

Supply Voltage (V_CC, V_CCQ

DC Input Voltage (V_I)

DC Output Voltage (V_O)

Outputs 3-STATE

)

−0.5V to +7.0V

Supply Voltage V_CC

V_CC

3.15V to 3.45V

4.75V to 5.25V

1.35V to 1.65V

−0.5V to +7.0V

V_CCQ

Outputs Active (Note 5)

−0.5V to V_CC+ 0.5V

Bus Termination Voltage (V_TT

)

DC Output Sink Current into

A-Port I_OL

Input Voltage (V_I)

64 mA

on A-Port and Control Pins

0.0V to 5.5V

DC Output Source Current from

A-Port I_OH

HIGH Level Output Current (I_OH

A-Port

)

−64 mA

−32 mA

DC Output Sink Current

LOW Level Output Current (I_OL

A-Port

)

into B-Port in the LOW State,

I_OL

+32 mA

+34 mA

80 mA

B-Port

DC Input Diode Current (I_IK

)

Operating Temperature (T_A)

−40°C to +85°C

V_I< 0V

−50 mA

Note 4: The Absolute Maximum Ratings are those values beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristic tables are not guaranteed at the absolute maximum rating.

The “Recommended Operating Conditions” table will define the conditions

for actual device operation.

DC Output Diode Current (I_OK

)

_O< 0V

−50 mA

+50 mA

_O> V_CC

Storage Temperature (T_STG

ESD Performance

)

−65°C to +150°C

>2000V

Note 5: I Absolute Maximum Rating must be observed.

Note 6: Unused inputs must be held high or low.

www.fairchildsemi.com

DC Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range, V

= 1.0V (Unless Otherwise Noted).

REF

Symbol

Test Conditions

Min

Typ

Max

Units

(Note 7)

B-Port

Others

B-Port

Others

+0.1

REF

2.0

0.0

−0.1

REF

0.8

1.0

REF

= 3.15V,

I = −18 mA

−1.2

= 4.75V

CCQ

A-Port

, V

= Min to Max (Note 8)

= −100 µA

= −8 mA

= −32 mA

= 100 µA

= 32 mA

− 0.2

CCQ

= 3.15V

2.4

2.0

= 4.75V

CCQ

, V

= Min to Max (Note 8)

0.2

0.5

CCQ

= 3.15V

= 4.75V

CCQ

B-Port

= 3.15V V

= 4.75V

= 34 mA

0.65

±10

CCQ

Control Pins

A-Port

, V

= 0 or Max

V = 5.5V or 0V

µA

CCQ

= 3.45V

V = 5.5V

= 5.25V

V = V

µA

CCQ

V = 0

−30

B-Port

= 3.45V

V = V

I CCQ

= 5.25V

V = 0

−5

CCQ

A-Port

= V

= 0

V or V = 0 to 4.5V

100

µA

OFF

CCQ

= 3.15V,

V = 0.8V

I(hold)

= 4.75V

V = 2.0V

−20

CCQ

A-Port

B-Port

A-Port

B-Port

A or B

Ports

= 3.45V,

= 3.45V

= 1.5V

= 0

µA

OZH

OZL

CCQ

= 5.25V

CCQ

= 3.45V,

−20

−10

= 5.25V

= 0.65V

CCQ

= 3.45V,

Outputs HIGH

Outputs LOW

)

CCQ

= 5.25V,

CCQ

= 0,

V = V

or GND

Outputs Disabled

Outputs HIGH

Outputs LOW

CCQ

A or B

Ports

V = 3.45V,

)

= 5.25V,

CCQ

= 0,

V = V

or GND

Outputs Disabled

One Input at 2.7V

CCQ

∆I

A-Port and

= 3.45V,

(Note 9)

Control Pins

V = 5.25V,

CCQ

A or Control Inputs at

or GND

Control Pins

A-Port

V = V

or 0

CCQ

V = V

I/O

B-Port

V = V

Note 7: All typicaI values are at V = 3.3V, V

= 5.0V, and T = 25°C.

CCQ

Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.

Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.

www.fairchildsemi.com

AC Operating Requirements

Over recommended ranges of supply voltage and operating free-air temperature, V

Symbol

= 1.0V (unless otherwise noted).

REF

Min

175

3.0

3.2

0.5

3.1

1.3

3.7

0.4

1.0

1.5

0.0

0.5

0.0

1.5

1.7

Max

Unit

MHz

Max Clock Frequency

Pulse Duration

CLOCK

LEAB or LEBA HIGH

CLKAB or CLKBA HIGH or LOW

A before CLKAB↑

B before CLKBA↑

A before LEAB↓

Setup Time

B before LEBA↓

CEAB before CLKAB↑

CEBA before CLKBA↑

A after CLKAB↑

Hold Time

B after CLKBA↑

A after LEAB↓

B after LEBA↓

CEAB after CLKAB↑

CEBA after CLKBA↑

AC Electrical Characteristics

Over recommended range of supply voltage and operating free-air temperature, V

= 1.0V (unless otherwise noted).

REF

_L= 30 pF for B-Port and C_L= 50 pF for A-Port.

Symbol From

(Output)

Min

Typ

(Note 10)

4.3

Max

Unit

(Input)

1.0

1.8

1.5

1.8

1.5

1.6

1.3

6.5

8.2

6.7

8.6

6.7

8.7

6.2

9.8

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

RISE

FALL

PLH

PHL

PLH

PHL

PLH

PHL

5.0

LEAB

CLKAB

OEAB

4.5

5.3

4.6

5.4

4.4

6.1

Transition time, B outputs (20% to 80%)

2.6

2.0

1.4

2.1

1.9

2.3

2.2

1.5

1.9

5.6

8.2

7.2

6.3

5.0

6.8

5.2

6.2

7.9

5.0

LEBA

CLKBA

OEBA

4.2

3.3

4.4

3.5

, t

5.0

PZH PZL

, t

3.9

PHZ PLZ

Note 10: All typical values are at V = 3.3V, V

= 5.0V, and T = 25°C.

CCQ

www.fairchildsemi.com

Test Circuits and Timing Waveforms

Test Circuit for A Outputs

Test Circuit for B Outputs

_Lincludes probes and jig capacitance.

C_Lincludes probes and jig capacitance.

For B-Port outputs, C_L= 30 pF is used for

worst case edge rate.

Voltage Waveforms Pulse Duration

(Vm = 1.5V for A-Port and 1.0V for B-Port)

Voltage Waveforms Propagation Delay Times

(A-Port to B-Port)

Voltage Waveforms Propagation Delay Times

(B-Port to A-Port)

Voltage Waveforms Setup and Hold Times

(Vm = 1.5V for A-Port and 1.0V for B-Port)

All input pulses have the following characteristics: frequency = 10 MHz, t = t = 2 ns, Z_O= 50Ω. The outputs are measured one at a time with

one transition per measurement.

Voltage Waveforms Enable and Disable Times (A-Port)

Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with

internal conditions such that the output is high except when disabled by the output control. All input pulses have the following characteristics: frequency = 10

MHz, t = t = 2 ns, Z = 50Ω. The outputs are measured one at a time with one transition per measurement.

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package, JEDEC MO-118 0.300” Wide

Package Number MS56A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide

Package Number MTD56

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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GTLP16612A产品参数

型号:	GTLP16612A
生命周期：	Obsolete
IHS 制造商：	PERICOM SEMICONDUCTOR CORP
零件包装代码：	TSSOP
包装说明：	TSSOP,
针数：	56
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.41
系列：	GTLP
JESD-30 代码：	R-PDSO-G56
JESD-609代码：	e0
长度：	14 mm
逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER
位数：	18
功能数量：	1
端口数量：	2
端子数量：	56
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	OPEN-DRAIN/3-STATE
输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：	8.7 ns
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.45 V
最小供电电压 (Vsup)：	3.15 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	TIN LEAD
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
宽度：	6.1 mm
Base Number Matches：	1

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