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产品型号HCPL-7840的概述

HCPL-7840芯片概述 HCPL-7840是一款高性能的光隔离器件，由阿尔特拉（Avago Technologies）公司设计和制造。广泛应用于电力电子、新能源、工业控制和通信等领域，其主要作用是实现信号的光电隔离，以确保不同电气等级之间的安全和可靠性。该芯片具有优良的性能指标，支持高速数据传输，同时提供有效的电气隔离，具有良好的抗干扰能力。 HCPL-7840的详细参数 HCPL-7840具备多种参数以满足不同应用需求。以下是一些核心参数： - 输入电流（IF）: 适用范围通常为10mA至20mA，为保证光电隔离效果所需的最小输入电流。 - 输出电流（VOH）: 当输入信号为逻辑高时，芯片能够提供高达20mA的输出电流，以满足负载需求。 - 光耦电阻（Riso）: 在测试条件下提供至多3000V的电气隔离。 - 传输延迟（td）: 通常在0.5至1.0毫秒之间，适用于高速信号传输...

产品型号HCPL-7840的Datasheet PDF文件预览

Analog Isolation Amplifier

Technical Data

HCPL-7840

Features

Description

environments such as those

generated by the high switching

rates of power IGBTs.

• High Common Mode

Rejection (CMR): 15 kV/µs

at V_CM= 1000V

• 5% Gain Tolerance

• 0.1% Nonlinearity

• Low Offset Voltage and Off-

set Temperature Coefficient

• 100 kHz Bandwidth

• Performance Specified Over

-40°C to 85°C Temperature

Range

• Recognized Under UL 1577

and CSA Approved for

Dielectric Withstand Proof

Test Voltage of 2500 Vac, 1

Minute

The HCPL-7840 isolation ampli-

fier provides accurate, electrically

isolated and amplified representa-

tions of voltage and current.

Low offset voltage together with

a low offset voltage temperature

coefficient permits accurate use

of auto-calibration techniques.

When used with a shunt resistor

in the current path, the HCPL-

7840 offers superior reliability,

cost effectiveness, size and

autoinsertability compared with

the traditional solutions such as

current transformers and Hall-

effect sensors.

Gain tolerance of 5% with 0.1%

nonlinearity further provide the

performance necessary for

accurate feedback and control.

A wide operating temperature

range with specified performance

allows the HCPL-7840 to be used

in hostile industrial environments.

The HCPL-7840 consists of a

sigma-delta analog-to-digital

converter optically coupled to a

digital-to-analog converter.

• Standard 8-Pin DIP Package

Superior performance in design

critical specifications such as

common-mode rejection, offset

voltage, nonlinearity, operating

temperature range and regulatory

compliance make the HCPL-7840

the clear choice for designing

reliable, lower-cost, reduced-size

products such as motor

Functional Diagram

Applications

• Motor Phase and Rail

Current Sensing

• Inverter Current Sensing

• Switched Mode Power

Supply Signal Isolation

DD2

DD1

DD2

IN+

OUT+

–

IN–

–

OUT–

• General Purpose Current

Sensing and Monitoring

GND1

GND2

SHIELD

controllers and inverters.

• General Purpose Analog

Signal Isolation

Common-mode rejection of

15 kV/µs makes the HCPL-7840

suitable for noisy electrical

A 0.1 F bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation which may be induced by ESD.

1-248

5965-4784E

Ordering Information

HCPL-7840#xxx

No option = Standard DIP Package, 50 per tube

300 = Gull Wing Surface Mount Lead Option, 50 per tube

500 = Tape/Reel Package Option (1 K min.), 1000 per reel

Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for

more information.

Package Outline Drawings

Standard DIP Package

9.65 ± 0.25

(0.380 ± 0.010)

DATE CODE

HP 7840

YYWW

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

0.20 (0.008)

0.33 (0.013)

5° TYP.

1.080 ± 0.320

(0.043 ± 0.013)

0.65 (0.025) MAX.

2.54 ± 0.25

(0.100 ± 0.010)

Gull Wing Surface Mount Option 300

PAD LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25

(0.380 ± 0.010)

1.016 (0.040)

1.194 (0.047)

4.826

TYP.

(0.190)

HP 7840

YYWW

6.350 ± 0.25

(0.250 ± 0.010)

9.398 (0.370)

9.960 (0.390)

0.381 (0.015)

0.635 (0.025)

1.194 (0.047)

1.778 (0.070)

9.65 ± 0.25

(0.380 ± 0.010)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

7.62 ± 0.25

(0.300 ± 0.010)

0.20 (0.008)

0.33 (0.013)

4.19

MAX.

(0.165)

0.635 ± 0.25

(0.025 ± 0.010)

1.080 ± 0.320

(0.043 ± 0.013)

0.635 ± 0.130

(0.025 ± 0.005)

12° NOM.

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED):

LEAD COPLANARITY

MAXIMUM: 0.102 (0.004)

xx.xx = 0.01

xx.xxx = 0.005

1-249

Maximum Solder Reflow Thermal Profile

Regulatory Information

The HCPL-7840 has been

approved by the following

organizations:

260

240

∆T = 145°C, 1°C/SEC

220

200

180

160

140

120

100

∆T = 115°C, 0.3°C/SEC

UL Recognized under UL 1577,

Component Recognition

Program, File E55361.

CSA Approved under CSA

Component Acceptance Notice

#5, File CA 88324.

∆T = 100°C, 1.5°C/SEC

TIME – MINUTES

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

Insulation and Safety Related Specifications

Parameter

Symbol Value Units

Conditions

Min. External Air Gap

(External Clearance)

Min. External Tracking Path

(External Creepage)

Min. Internal Plastic Gap

(Internal Clearance)

L(IO1)

7.1

Measured from input terminals to output

terminals, shortest distance through air.

Measured from input terminals to output

terminals, shortest distance path along body.

Through insulation distance, conductor to

conductor, usually the direct distance

between the photoemitter and photodetector

inside the optocoupler cavity.

L(IO2)

7.4

0.08

Tracking Resistance

(Comparative Tracking Index)

Isolation Group

CTI

200

IIIa

Volts DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter

Storage Temperature

Ambient Operating Temperature

Supply Voltages

Symbol

T_S

Min.

-55

-40

Max.

125

Unit

°C

Note

T_A

V_DD1, V_DD2

0.0

5.5

Steady-State Input Voltage

2 Second Transient Input Voltage

Output Voltages

Lead Solder Temperature

(10 sec., 1.6 mm below seating plane)

_IN+, V

-2.0

-6.0

-0.5

V_DD1+0.5

IN-

V_OUT+, V_OUT-

T_LS

V_DD2+0.5

260

°C

Solder Reflow Temperature Profile

See Maximum Solder Reflow Thermal Profile Section

1-250

Recommended Operating Conditions

Parameter

Ambient Operating Temperature

Supply Voltages

Symbol

Min.

-40

4.5

Max.

5.5

Unit

°C

Note

T_A

V_DD1, V_DD2

Input Voltage

_IN+,V

-200

200

IN-

DC Electrical Specifications

All specifications, typicals and figures are at the nominal operating conditions of V_IN+= 0 V, V_IN-= 0 V,

T_A= 25°C, V_DD1= 5 V and V_DD2= 5 V, unless otherwise noted.

Parameter

Symbol Min. Typ. Max. Unit

Test Conditions

Fig. Note

Input Offset Voltage

V_OS

-1.2 -0.2 1.0 mV

-3.0 -0.2 2.0

1,2,3

-40°C ≤ T_A≤ 85°C

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

Gain

7.60 8.00 8.40 V/V -200 ≤ V_IN+≤ 200 mV

7.44 8.00 8.56

-200 ≤ V_IN+≤ 200 mV

-40°C ≤ T_A≤ 85°C

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

5,6,7

200 mV Nonlinearity

100 mV Nonlinearity

NL₂₀₀

NL₁₀₀

0.1

0.2

0.4

-200 ≤ V_IN+≤ 200 mV

5, 8

5,8,9

10,12

-200 ≤ V_IN+≤ 200 mV

-40°C ≤ T_A≤ 85°C

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

0.05 0.1

0.2

-100 ≤ V_IN+≤ 100 mV

5, 8

5,8,9

11,12

-100 ≤ V_IN+≤ 100 mV

-40°C ≤ T_A≤ 85°C

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

Maximum Input Voltage

Before Output Clipping

320

IN+

MAX

Average Input Bias Current

Average Input Resistance

Input DC Common-Mode

Rejection Ratio

I_IN

R_IN

CMRR_IN

-0.57

480

µA

kΩ

Output Resistance

Output Low Voltage

Output High Voltage

Output Common-Mode

Voltage

Input Supply Current

Output Supply Current

Output Short-Circuit Current |I_OSC

R_O

V_OL

V_OH

V_OCM

1.28

3.84

Ω

_IN+= 400 mV

V_IN+= -400 mV

-400 < V_IN+< 400 mV

-40°C ≤ T_A≤ 85°C

2.20 2.56 2.80

I_DD1

I_DD2

8.7 15.5 mA 4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V 14

8.8 14.5 mA

11 mA V_OUT= 0 V or V_DD2

1-251

AC Electrical Specifications

All specifications, typicals and figures are at the nominal operating conditions of V_IN+= 0 V, V_IN-= 0 V,

T_A= 25°C, V_DD1= 5 V and V_DD2= 5 V, unless otherwise noted.

Parameter

Common Mode

Rejection

Symbol Min. Typ. Max. Unit

Test Conditions

kV/µs V_CM= 1 kV

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

Fig. Note

CMR

Common Mode

Rejection Ratio

at 60 Hz

CMRR

>140

Propagation Delay

to 50%

t_PD50

3.7

6.5

µs

_IN+= 0 to 100 mV step

17,18

-40°C ≤ T_A≤ 85°C

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

Propagation Delay

to 90%

Rise/Fall Time

(10-90%)

t_PD90

t_R/F

5.7

3.4

9.9

6.6

Small-Signal

Bandwidth

(-3 dB)

f_{-3 dB}

100

kHz

-40°C ≤ T_A≤ 85°C

4.5 ≤ (V_DD1, V_DD2) ≤ 5.5 V

17, 19,

Small-Signal

Bandwidth (-45°)

RMS Input-

Referred Noise

Power Supply

Rejection

f_-45°

V_N

0.6

570

mV_rmsIn recommended

application circuit

mV_P-P

21, 23

PSR

Package Characteristics

All specifications, typicals and figures are at the nominal operating conditions of V_IN+= 0 V, V_IN-= 0 V,

T_A= 25°C, V_DD1= 5 V and V_DD2= 5 V, unless otherwise noted.

Parameter

Symbol Min. Typ. Max. Unit

Test Conditions

Fig. Note

Input-Output Momentary

Withstand Voltage*

Input-Output Resistance

Input-Output Capacitance

2500

V_rms

t = 1 min., RH ≤ 50%

12,13

ISO

R_I-O

C_I-O

10¹²

0.6

Ω

_I-O= 500 Vdc

f = 1 MHz

_I-O= 0 Vdc

*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating, refer to the VDE 0884 Insulation Characteristics Table (if applicable),

your equipment level safety specification, or HP Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”

1-252

Notes:

7. Short-circuit current is the amount of

output current generated when either

output is shorted to V_DD2or ground.

HP does not recommend operation

under these conditions.

delta quantization noise. Chopper

noise results from chopper stabiliza-

tion of the output op-amps. It occurs

at a specific frequency (typically 500

kHz) and is not attenuated by the on-

chip output filter. The on-chip filter

does eliminate most, but not all, of

the sigma-delta quantization noise.

An external filter circuit may be

easily added to the external post-

amplifier to reduce the total RMS

output noise. See applications section

for more information.

1. If V_IN-is brought above V_DD1- 2 V

with respect to GND1 an internal test

mode may be activated. This test

mode is not intended for customer

use.

2. Exact offset value is dependent on

layout of external bypass capacitors.

The offset value in the data sheet

corresponds to HP’s recommended

layout (see Figures 25 and 26).

3. Nonlinearity is defined as half of the

peak-to-peak output deviation from

the best-fit gain line, expressed as a

percentage of the full-scale differen-

tial output voltage.

8. CMR (also known as IMR or Isolation

Mode Rejection) specifies the

minimum rate of rise of a common

mode noise signal applied across the

isolation boundary at which small

output perturbations begin to appear.

These output perturbations can occur

with both the rising and falling edges

of the common mode waveform and

may be of either polarity. A CMR

failure is defined as a perturbation

exceeding 200 mV at the output of

the recommended application circuit

(Figure 23). See applications section

for more information on CMR.

11. Data sheet value is the amplitude of

the transient at the differential output

of the HCPL-7840 when a 1 V_P-P

4. Because of the switched capacitor

nature of the sigma-delta A/D

converter, time-averaged values are

shown.

1 MHz square wave with 100 ns rise

and fall times (measured at pins 1

and 8) is applied to both V_DD1and

V_DD2

5. CMRR_INis defined as the ratio of the

gain for differential inputs applied

between pins 2 and 3 to the gain for

common mode inputs applied to both

pins 2 and 3 with respect to pin 4.

6. When the differential input signal

exceeds approximately 320 mV, the

outputs will limit at the typical values

shown.

9. CMRR is defined as the ratio of

differential signal gain (signal applied

differentially between pins 2 and 3)

to the common mode gain (input pins

tied to pin 4 and the signal applied

between the input and the output of

the isolation amplifier) at 60 Hz,

expressed in dB.

12. In accordance with UL1577, each

isolation amplifer is proof tested by

applying an insulation test voltage

≥ 3000 V_RMSfor 1 second (leakage

current detection limit I_I-O≤ 5 µA).

13. Device considered a two terminal

device: Pins 1, 2, 3 and 4 connected

together; pins 5, 6, 7 and 8

10. Output noise comes from two primary

sources: chopper noise and sigma-

connected together.

DD2

DD1

+15 V

0.1 µF

10 K

HCPL-7840

OUT

0.1 µF

10 K

–

AD624CD

GAIN = 100

0.1 µF

0.47

µF

0.47

µF

-15 V

Figure 1. Input Offset Voltage Test Circuit.

0.3

0.2

0.1

4.0

3.5

0.6

vs. V

= 5 V)

DD1 DD2

= 5 V

DD1

DD2

0.4

0.2

DD2 DD1

NEGATIVE

OUTPUT

POSITIVE

OUTPUT

3.0

2.5

2.0

= 25°C

-0.2

-0.4

= 5 V

= 25°C

DD1

DD2

1.5

1.0

-0.6

-0.8

-0.1

-40 -20

20 40 60

80 100

4.4

4.6

4.8

5.0

5.2

5.4

5.6

-0.6 -0.4 -0.2

0.2

0.4

0.6

– TEMPERATURE – °C

– SUPPLY VOLTAGE – V

– INPUT VOLTAGE – V

Figure 2. Input Offset Change vs.

Temperature.

Figure 3. Input Offset Change vs.

V_DD1and V_DD2

Figure 4. Output Voltages vs. Input

Voltage.

1-253

DD1

DD2

+15 V

0.1 µF

10 K

404

HCPL-7840

OUT

13.2

10 K

–

AD624CD

GAIN = 4

AD624CD

GAIN = 10

0.01 µF

0.1 µF

0.47

µF

0.47

µF

-15 V

10 K

0.47

µF

Figure 5. Gain and Nonlinearity Test Circuit.

0.1

0.15

0.10

0.05

0.10

0.08

0.06

0.04

0.02

200 mV ERROR

100 mV ERROR

vs. V

DD1 DD2

= 5 V)

vs. V (V

DD2 DD1

= 5 V

= 0 V

DD1

DD2

= 25°C

-0.1

-0.2

-0.3

IN–

= 25°C

= 5 V

DD1

DD2

-0.02

-0.05

-0.10

-0.4

-0.5

-0.04

-0.06

-40 -20

20 40 60

80 100

-0.2

-0.1

0.1

0.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

– TEMPERATURE – °C

– INPUT VOLTAGE – V

– SUPPLY VOLTAGE – V

IN+

Figure 6. Gain Change vs.

Temperature.

Figure 7. Gain Change vs. V_DD1and

V_DD2

Figure 8. Nonlinearity Error Plot vs.

Input Voltage.

0.20

0.12

0.060

vs. V

DD1 DD2

= 5 V)

vs. V

DD1 DD2

= 5 V)

200 mV NL

100 mV NL

DD2 DD1

vs. V (V

DD2 DD1

0.15

0.10

0.11

0.10

0.055

0.050

= 25°C

T = 25°C

= 5 V

DD1

DD2

= 0 V

IN–

= 25 °C

0.05

0.09

0.08

0.045

0.040

-40 -20

20 40

60 80 100

4.4

4.6

4.8

5.0

5.2

5.4

5.6

4.4

4.6

4.8

5.0

5.2

5.4

5.6

– TEMPERATURE – °C

– SUPPLY VOLTAGE – V

Figure 9. Nonlinearity vs.

Temperature.

Fibure 10. 200 mV Nonlinearity vs.

_DD1and V_DD2

Figure 11. 100 mV Nonlinearity vs.

_DD1and V_DD2

1-254

= 85°C

= 25°C

= -40°C

= 85°C

= 25°C

= -40°C

5.00

0.50

-2

-4

-6

= 5 V

= 0 V

DD1

DD2

IN–

= 5 V

= 0 V

DD1

DD2

IN–

= 25°C

0.05

0.01

= 5 V

-8

DD1

DD2

-10

-6

-4

-2

±0.10

±0.20

±0.30

±0.40

-0.4

-0.2

V – INPUT VOLTAGE – V

IN+

0.2

0.4

– INPUT VOLTAGE – V

FS – FULL-SCALE INPUT VOLTAGE – V

IN+

Figure 12. Nonlinearity vs. Full-Scale

Input Voltage.

Figure 13. Input Current vs. Input

Voltage.

Figure 14. Input Supply Current vs.

Input Voltage.

10 K

150 pF

DD2

78L05

+15 V

IN OUT

0.1 µF

10.0

0.1

µF

0.1

µF

= 5 V

= 0 V

DD1

DD2

IN–

0.1 µF

2 K

9.5

–

HCPL-7840

9 V

OUT

MC34081

0.1 µF

9.0

8.5

8.0

= 85°C

= 25°C

= -40°C

10 K

150

PULSE GEN.

-15 V

-0.4

-0.2

0.2

0.4

–

– INPUT VOLTAGE – V

IN+

Figure 16. Common Mode Rejection

Test Circuit.

Figure 15. Output Supply Current vs.

Input Voltage.

10 K

DD2

DD1

+15 V

0.1 µF

DELAY TO 90%

DELAY TO 50%

RISE/FALL TIME

0.1 µF

2 K

–

HCPL-7840

OUT

MC34081

0.1 µF

0.01 µF

= 5 V

10 K

DD1

DD2

= 0 V

IN–

IN+

= 0 TO 100 mV STEP

60 80 100

– TEMPERATURE – °C

-15 V

-40 -20

20 40

IMPEDANCE LESS THAN 10 Ω.

Figure 18. Propagation Delays and

Rise/Fall Time vs. Temperature.

Figure 17. Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit.

1-255

2.5

160

140

= 200 mV

= 100 mV

= 0 mV

IN+

= 5 V

DD1

DD2

2.0

1.5

-1

= 5 V

= 25 °C

DD1

DD2

= 25°C

= 5 V

120

100

DD1

DD2

= 5 V

-2

-3

-4

1.0

0.5

50 100

f – FREQUENCY – KHz

500

50 100

500

-40 -20

20 40

60 80 100

f – FREQUENCY – kHz

– TEMPERATURE – °C

Figure 19. Amplitude Response vs.

Frequency.

Figure 20. 3 dB Bandwidth vs.

Temperature

Figure 21. RMS Input-Referred Noise

vs. Recommended Application Circuit

Bandwidth.

Applications Information

Functional Description

finally, the differential output of

the isolation amplifier is

required because of the high-

speed digital nature of the signals

inside the isolation amplifier. A

0.01 µF bypass capacitor (C3) is

also recommended at the input

pin(s) due to the switched-

capacitor nature of the input

circuit. The input bypass capaci-

tor should be at least 1000 pF to

maintain gain accuracy of the

isolation amplifier.

converted to a ground-referenced

single-ended output voltage with

a simple differential amplifier

circuit (U3 and associated com-

ponents). Although the applica-

tion circuit is relatively simple, a

few recommendations should be

followed to ensure optimal

performance.

Figure 22 shows the primary

functional blocks of the HCPL-

7840. In operation, the sigma-

delta modulator converts the

analog input signal into a high-

speed serial bit stream. The time

average of this bit stream is

directly proportional to the input

signal. This stream of digital data

is encoded and optically trans-

mitted to the detector circuit. The

detected signal is decoded and

converted back into an analog

signal, which is filtered to obtain

the final output signal.

Supplies and Bypassing

Inductive coupling between the

input power-supply bypass

capacitor and the input circuit,

including the input bypass

As mentioned above, an inexpen-

sive 78L05 three-terminal

regulator can be used to reduce

the gate-drive power supply

voltage to 5 V. To help attenuate

high frequency power supply

noise or ripple, a resistor or

inductor can be used in series

with the input of the regulator to

form a low-pass filter with the

regulator’s input bypass

capacitor and the input leads of

the HCPL-7840, can introduce

additional DC offset in the circuit.

Several steps can be taken to

minimize the mutual coupling

between the two parts of the

circuit, thereby improving the

offset performance of the design.

Separate the two bypass

capacitors C2 and C3 as much as

possible (even putting them on

opposite sides of the PC board),

while keeping the total lead

lengths, including traces, of each

bypass capacitor less than 20

mm. PC board traces should be

made as short as possible and

Application Circuit

The recommended application

circuit is shown in Figure 23. A

floating power supply (which in

many applications could be the

same supply that is used to drive

the high-side power transistor) is

regulated to 5 V using a simple

three-terminal voltage regulator

(U1). The voltage from the cur-

rent sensing resistor, or shunt

(Rsense), is applied to the input

of the HCPL-7840 through an RC

anti-aliasing filter (R5, C3). And

capacitor.

As shown in Figure 23, 0.1 µF

bypass capacitors (C2, C4)

should be located as close as

possible to the input and output

power supply pins of the HCPL-

7840. The bypass capacitors are

1-256

placed close together or over

ground plane to minimize loop

area and pickup of stray magnetic

fields. Avoid using sockets, as

they will typically increase both

loop area and inductance. And

finally, using capacitors with

small body size and orienting

them perpendicular to each other

on the PC board can also help.

For more information concerning

this effect, see Application Note

1078, Designing with Hewlett-

Packard Isolation Amplifiers.

shunt with a lower tempco can

help minimize this effect. The

Application Note 1078, Design-

ing with Hewlett-Packard

Isolation Amplifiers, contains

additional information on

input bypass capacitor, and the

wires or traces connecting the

two. Undamped ringing of the

input circuit near the input

sampling frequency can alias into

the baseband producing what

might appear to be noise at the

output of the device. To be

effective, the damping resistor

should be at least 39 Ω.

designing with current shunts.

The recommended method for

connecting the isolation amplifier

to the shunt resistor is shown in

Figure 23. Pin 2 (V_IN+) is con-

nected to the positive terminal of

the shunt resistor, while pin 3

PC Board Layout

In addition to affecting offset, the

layout of the PC board can also

affect the common mode rejec-

tion (CMR) performance of the

isolation amplifier, due primarily

to stray capacitive coupling

between the input and the output

circuits. To obtain optimal CMR

performance, the layout of the

printed circuit board (PCB)

should minimize any stray coup-

ling by maintaining the maximum

possible distance between the

input and output sides of the

circuit and ensuring that any

ground plane on the PCB does

not pass directly below the

HCPL-7840. Using surface mount

components can help achieve

many of the PCB objectives

(V ) is shorted to pin 4 (GND1),

IN-

Shunt Resistor Selection

with the power-supply return

path functioning as the sense line

to the negative terminal of the

current shunt. This allows a

The current-sensing shunt resis-

tor should have low resistance (to

minimize power dissipation), low

inductance (to minimize di/dt

induced voltage spikes which

could adversely affect operation),

and reasonable tolerance (to

maintain overall circuit accuracy).

The value of the shunt should be

chosen as a compromise between

minimizing power dissipation by

making the shunt resistance

smaller and improving circuit

accuracy by making it larger and

utilizing the full input range of

the HCPL-7840. Hewlett-Packard

recommends four different shunts

which can be used to sense

average currents in motor drives

up to 35 A and 35 hp. Table 1

shows the maximum current and

horsepower range for each of the

LVR-series shunts from Dale.

Even higher currents can be

sensed with lower value shunts

available from vendors such as

Dale, IRC, and Isotek (Isabellen-

huette). When sensing currents

large enough to cause significant

heating of the shunt, the tempera-

ture coefficient of the shunt can

introduce nonlinearity due to the

signal dependent temperature

rise of the shunt. Using a heat

sink for the shunt or using a

single pair of wires or PC board

traces to connect the isolation

amplifier circuit to the shunt

resistor. In some applications,

however, supply currents flowing

through the power-supply return

path may cause offset or noise

problems. In this case, better

performance may be obtained by

connecting pin 3 to the negative

terminal of the shunt resistor

separate from the power supply

return path. When connected this

way, both input pins should be

bypassed. Whether two or three

wires are used, it is recom-

discussed in the preceding para-

graphs. An example through-hole

PCB layout illustrating some of

the more important layout

recommendations is shown in

Figures 25 and 26. See Applica-

tion Note 1078, Designing with

Hewlett-Packard Isolation

mended that twisted-pair wire or

very close PC board traces be

used to connect the current shunt

to the isolation amplifier circuit

to minimize electromagnetic

interference to the sense signal.

Amplifiers, for more information

on PCB layout considerations.

The 68 Ω resistor in series with

the input lead forms a low-pass

anti-aliasing filter with the input

bypass capacitor with a 200 kHz

bandwidth. The resistor performs

another important function as

well; it dampens any ringing

Post-Amplifier Circuit

The recommended application

circuit (Figure 23) includes a

post-amplifier circuit that serves

three functions: to reference the

output signal to the desired level

(usually ground), to amplify the

signal to appropriate levels, and

which might be present in the

circuit formed by the shunt, the

1-257

to help filter output noise. The

particular op-amp used in the

post-amp is not critical; however,

it should have low enough offset

and high enough bandwidth and

slew rate so that it does not

adversely affect circuit perfor-

mance. The offset of the op-amp

should be low relative to the out-

put offset of the HCPL-7840, or

less than about 5 mV.

between low noise and fast

response times. The overall

recommended application circuit

has a bandwidth of 66 kHz, a rise

time of 5.2 µs and delay to 90%

of 8.5 µs.

how the output noise changes as

a function of the post-amplifier

bandwidth. The post-amplifier

circuit exhibits a first-order low-

pass filter characteristic. For the

same filter bandwidth, a higher-

order filter can achieve even

better attenuation of modulation

noise due to the second-order

noise shaping of the sigma-delta

modulator. For more information

on the noise characteristics of the

HCPL-7840, see Application Note

1078, Designing with Hewlett-

Packard Isolation Amplifiers.

The gain-setting resistors in the

post-amp should have a tolerance

of 1% or better to ensure adequate

CMRR and gain tolerance for the

overall circuit. Resistor networks

with even better ratio tolerances

can be used which offer better

performance, as well as reducing

the total component count and

board space.

To maintain overall circuit band-

width, the post-amplifier circuit

should have a bandwidth at least

twice the minimum bandwidth of

the isolation amplifier, or about

200 kHz. To obtain a bandwidth

of 200 kHz with a gain of 5, the

op-amp should have a gain-

The HCPL-7840 can also be used

to isolate signals with amplitudes

larger than its recommended

input range through the use of a

resistive voltage divider at its

input. The only restrictions are

that the impedance of the divider

be relatively small (less than

1 KΩ so that the input resistance

(480 KΩ ) and input bias current

(0.6 A) do not affect the accuracy

of the measurement. An input

bypass capacitor is still required,

although the 68 Ω series damping

resistor is not (the resistance of

the voltage divider provides the

same function). The low pass

filter formed by the divider

The post-amplifier circuit can be

easily modified to allow for

bandwidth greater than 1 MHz.

The post-amplifier circuit

single-supply operation. Figure

24 shows a schematic for a post

amplifier for use in 5 V single

supply applications. One addi-

tional resistor is needed and the

gain is decreased to 1 to allow

circuit operation over the full

input voltage range. See Applica-

tion Note 1078, Designing with

Hewlett-Packard Isolation

includes a pair of capacitors (C5

and C6) that form a single-pole

low-pass filter. These capacitors

allow the bandwidth of the post-

amp to be adjusted independently

of the gain and are useful for

reducing the output noise from

the isolation amplifier (doubling

the capacitor values halves the

circuit bandwidth). The compo-

nent values shown in Figure 23

form a differential amplifier with

a gain of 5 and a cutoff frequency

of approximately 100 kHz and

were chosen as a compromise

Amplifiers, for more information

on the post-amplifier circuit.

Other Information

resistance and the input bypass

capacitor may limit the

achievable bandwidth.

As mentioned above, reducing the

bandwidth of the post amplifier

circuit reduces the amount of

output noise. Figure 21 shows

Table 1. Current Shunt Summary

Maximum

Power

Dissipation

Maximum

Average

Current

Maximum

Horsepower

Range

Shunt

Resistance

Shunt Resistor Part Number

LVR-3.05-1%

50 mΩ

20 mΩ

10 mΩ

5 mΩ

3 W

5 W

3 A

8 A

15 A

35 A

0.8-3.0 hp

2.2-8.0 hp

4.1-15 hp

9.6-35 hp

LVR-3.02-1%

LVR-3.01-1%

LVR-5.005-1%

1-258

VOLTAGE

CLOCK

VOLTAGE

REGULATOR

GENERATOR

REGULATOR

ISOLATION

BOUNDARY

Σ∆

LED DRIVE

CIRCUIT

DETECTOR

CIRCUIT

DECODER

AND D/A

ISO-AMP

OUTPUT

ISO-AMP

INPUT

ENCODER

FILTER

MODULATOR

Figure 22. HCPL-7840 Block Diagram.

POSITIVE

FLOATING

SUPPLY

150 pF

HV+

GATE DRIVE

CIRCUIT

• • •

10.0 K

78L05

+5 V

+15 V

OUT

0.1 µF

0.1

µF

0.1

µF

–

2.00 K

OUT

0.01

µF

MC34081

2.00 K

MOTOR

–

• • •

150 pF

10.0 K

0.1 µF

SENSE

HCPL-7840

-15 V

• • •

HV–

Figure 23. Recommended Application Circuit.

Figure 25. Top Layer of Printed

Circuit Board Layout.

150 pF

+5 V

TO V

DD1

10.0 K

TO V

DD2

OUT+

OUT–

TO R

SENSE+

SENSE–

+5 V

0.1 µF

R4A

20.0 K

Figure 26. Bottom Layer of Printed

Circuit Board Layout.

0.1 µF

10.0 K

–

OUT

MC34071

10.0 K

R4B

150 pF

20.0 K

HCPL-7840

Figure 24. Single-Supply Post-Amplifier Circuit.

1-259

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HCPL-7840产品参数

型号:	HCPL-7840
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	HEWLETT PACKARD CO
零件包装代码：	DIP
包装说明：	DIP, DIP8,.3
针数：	8
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
风险等级：	5.13
Is Samacsys：	N
放大器类型：	ISOLATION AMPLIFIER
标称带宽 (3dB)：	100 MHz
最大共模电压：	3750 V
最小绝缘电压：	3750 V
JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
电源：	5 V
认证状态：	Not Qualified
子类别：	Isolation Amplifiers
供电电压上限：	5.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
最大电压增益：	8.4
最小电压增益：	7.6
Base Number Matches：	1

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