HI-3599PSI原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

HI-3596, HI-3597, HI-3598, HI-3599

Octal ARINC 429 Receivers

with Label Recognition and SPI Interface

January, 2012

•ꢀ 32^ndbit can be data or parity

GENERAL DESCRIPTION

•ꢀ Low Power

The HI-359x family from Holt Integrated Circuits are sili-

con gate CMOS ICs for interfacing up to eight ARINC

429 receive buses to a high-speed Serial Peripheral

Interface (SPI) enabled microcontroller. Each receiver

has user-programmable label recognition for up to 16

labels, a four-word data buffer (FIFO), and an on-chip

analog line receiver. Receive FIFO status can be moni-

tored using the programmable external interrupt pins,

or by polling the status register. Other features include

theꢀabilityꢀtoꢀswitchꢀtheꢀbit-signiﬁanceꢀofꢀtheꢀARINCꢀ429ꢀ

label and to recognize the 32^ndreceived ARINC bit as

eitherꢀdataꢀorꢀaꢀparityꢀﬂag.ꢀSomeꢀversionsꢀprovideꢀaꢀdigi-

tal transmit channel which can be utilized with an exter-

nal line driver such as HI-8570 to relay information from

multiple sources, for example sensors, to a single col-

lectionꢀpointꢀsuchꢀasꢀaꢀﬂightꢀcomputerꢀandꢀcanꢀalsoꢀbeꢀ

conﬁguredꢀasꢀaꢀloopbackꢀtestꢀregisterꢀforꢀeachꢀreceiveꢀ

channel. Versions are also available with different input

resistanceꢀvaluesꢀtoꢀprovideꢀﬂexibilityꢀwhenꢀusingꢀexter-

nal lightning protection circuitry. The SPI and all control

signals are CMOS and TTL compatible and support

3.3V or 5V operation.

•ꢀ Industrial & extended temperature ranges

PIN CONFIGURATION (TOP VIEW)

ACLK - 1

39 - RIN8A

38 - RIN7B

37 - RIN7B-40

36 - RIN7A-40

35 - RIN7A

SCK - 2

__

CS - 3

SI - 4

SO - 5

MR - 6

TX1 - 7

HI-3598PQI

&

HI-3598PQT

34 - RIN6B

33 - RIN6B-40

32 - RIN6A-40

31 - RIN6A

TX0 - 8

RIN1A - 9

RIN1A-40 - 10

RIN1B-40 - 11

RIN1B - 12

- 13

30 - RIN5B

29 - RIN5B-40

28 - RIN5A-40

27 - RIN5A

The HI-3596 and HI-3598 are full featured parts. The

HI-3597 and HI-3599 give the user the option of utilizing

aꢀsmallerꢀ24-pinꢀSOICꢀpackageꢀwithꢀveryꢀlittleꢀtradeꢀoffꢀinꢀ

features.ꢀInꢀthisꢀcase,ꢀaꢀglobalꢀinterruptꢀﬂagꢀisꢀprovidedꢀ

instead of individual external FIFO interrupt pins. The

HI-3597 is identical to the HI-3599 except that it offers

the digital transmit feature and seven receive channels.

HI-3598 Full function, full pin-out version

52 - Pin Plastic Quad Flat Pack (PQFP)

ACLK - 1

SCK - 2

CS - 3

SI - 4

SO - 5

TX1 - 6

TX0 - 7

RIN2A - 8

RIN2B - 9

RIN3A - 10

RIN3B - 11

GND - 12

24 - VDD

23 - FLAG

22 - RIN8B

21 - RIN8A

20 - RIN7B

19 - RIN7A

18 - RIN6B

17 - RIN6A

16 - RIN5B

15 - RIN5A

14 - RIN4B

13 - RIN4A

FEATURES

HI-3597

PSI

•ꢀ ARINC 429 compliant

&

•ꢀ Up to 8 independent receive channels

•ꢀ Digital transmit channel (except HI-3599)

•ꢀ 3.3V or 5.0V logic supply operation

HI-3597

PST

•ꢀ On-chip analog line receivers connect directly to

HI-3597 minimum footprint, reduced pin-out version

24 - Pin Plastic Small Outline package (SOIC)

ARINC 429 bus

•ꢀ Programmable label recognition for 16 labels per

channel

(See page 13 for additional package pin conﬁgurations)

•ꢀ Independent data rate selection for each receiver

•ꢀ Four-wire SPI interface

•ꢀ Label bit-order control

HOLT INTEGRATED CIRCUITS

www.holtic.com

1

DS3598 Rev. C

01/12

HI-3596, HI-3597, HI-3598, HI-3599

BLOCK DIAGRAMS

HI-3596 & HI-3598

VDD

ACLK

SCK

SPI

Interface

CS

SI

SO

Status Register

FLAG

Transmit Register

TX1, TX0

MR

Ch 8

Ch 7

Ch 6

Ch 5

Ch 4

Ch 3

Ch 2

Channel 1

Control Register

16 Label

Filter

FLAG8

FLAG7

FLAG6

FLAG5

FLAG4

FLAG3

FLAG2

FLAG1

BUS 8

BUS 7

BUS 6

BUS 5

BUS 4

BUS 3

BUS 2

Memory

40 Kohm

ARINC 429

Received

Data FIFO

(4 words)

ARINC 429

valid word

checker

RIN1A

RIN1B

Label

Filter

ARINC 429

Bus 1

RIN1A-40

RIN1B-40

{

ARINC 429

Line Receiver

GND

NOTE:

RIN1A & RIN1B available only on HI-3596

RIN1A-40 & RIN1B-40 available only on HI-3596-40

HI-3597 & HI-3599 (24-pin versions)

VDD

ACLK

SCK

CS

SPI

SI

Interface

SO

Status Register

FLAG

Transmit Register

TX1, TX0

(HI-3597 only)

Ch 8

Ch 7

Ch 6

Ch 5

Ch 4

Ch 3

Ch 2

Channel 1

Control Register

16 Label

Filter

BUS 8

BUS 7

BUS 6

BUS 5

BUS 4

BUS 3

BUS 2

Memory

ARINC 429

Received

Data FIFO

(4 words)

40 Kohm

ARINC 429

valid word

checker

RIN1A*

RIN1B*

Label

Filter

ARINC 429

Bus 1

{

ARINC 429

Line Receiver

*NOTE: RIN1A & RIN1B

are not available

on HI-3597

The 40 Kohm resistors are shorted on the

HI-3597-40 and HI-3599-40

GND

Figure 1. BlockꢀDiagrams

HOLT INTEGRATED CIRCUITS

2

HI-3596, HI-3597, HI-3598, HI-3599

PIN DESCRIPTIONS

Table 1. Pin Descriptions

VDD

GND

Function Description

3596 3597 3598 3599

POWER 3.3V or 5.0V power supply

POWER Chip 0V supply

X

Chip select. Data is shifted into SI and out of SO when

CS is low

CS

INPUT

X

SPIꢀClock.ꢀDataꢀisꢀshiftedꢀintoꢀorꢀoutꢀofꢀtheꢀSPIꢀinterfaceꢀ

using SCK

SCK

INPUT

SI

INPUT

OUTPUT SPI interface serial data output

Master 1 MHz timing reference for the ARINC 429

SPI interface serial data input

X

SO

ACLK

INPUT

X

receiver and transmitter

ARINC ARINC receiver positive input. Direct connection to

INPUT ARINC 429 bus

RIN1A* - RIN8A

Std

-40

X

Std

-40

-

Std

-40

-

ARINC ARINC receiver negative input. Direct connection to

INPUT ARINC 429 bus

RIN1B* - RIN8B

ARINC Alternate ARINC receiver positive input. Requires

INPUT externalꢀ40KΩꢀresistor

RIN1A-40* - RIN8A-40

RIN1B-40* - RIN8B-40

FLAG1 - FLAG8

ARINC Alternate ARINC receiver negative input. Requires

INPUT

externalꢀ40KΩꢀresistor

Goes high when ARINC 429 receiver FIFO is not empty

(CR1=0), or full (CR1=1)

OUTPUT

FLAG

TX1

OUTPUT Logical OR of FLAG1 through FLAG8

X

-

OUTPUT ARINC 429 test word ONE state serial output pin

OUTPUT ARINC 429 test word ZERO state serial output pin

Hardware active high Master Reset. Clears all

TX0

-

MR

INPUT

receivers and FIFOs. Does not affect Control Register

contents.

X

-

X

-

* NOTE: RIN1A & RIN1B are not available on HI-3597

HOLT INTEGRATED CIRCUITS

3

HI-3596, HI-3597, HI-3598, HI-3599

lower four bits specify the op code, described in Table

INSTRUCTIONS

2.ꢀTheꢀfourꢀchannelꢀassignmentꢀbitsꢀareꢀ“don’tꢀcare”ꢀforꢀ

instructionsꢀthatꢀareꢀnotꢀchannel-speciﬁc,ꢀsuchꢀasꢀMas-

ter Reset.

Instruction op codes are used to read, write and con-

ﬁgureꢀ theꢀ HI-359xꢀ devices.ꢀ ꢀ Theꢀ instructionꢀ formatꢀ isꢀ

illustrated in Figure 2. When CS goes low, the next 8

clocksꢀatꢀtheꢀSCKꢀpinꢀshiftꢀanꢀinstructionꢀopꢀcodeꢀintoꢀ

theꢀdecoder,ꢀstartingꢀwithꢀtheꢀﬁrstꢀrisingꢀedge.ꢀꢀTheꢀopꢀ

codeꢀisꢀfedꢀintoꢀtheꢀSIꢀpin,ꢀmostꢀsigniﬁcantꢀbitꢀﬁrst.ꢀꢀ

ARINC 429

Channel

OP Code

MSB

7

6

5

4

3

2

1

0

LSB

Forꢀwriteꢀinstructions,ꢀtheꢀmostꢀsigniﬁcantꢀbitꢀofꢀtheꢀdataꢀ

word must immediately follow the instruction op code

andꢀisꢀclockedꢀintoꢀitsꢀregisterꢀonꢀtheꢀnextꢀrisingꢀSCKꢀ

edge. Data word length varies depending on word type

written: 16-bit Control Register writes, 32-bit transmit

registerꢀ writesꢀ orꢀ 128-bitꢀ writesꢀ toꢀ aꢀ channel’sꢀ label-

matching enable/disable memory.

SPI INSTRUCTION FORMAT

Example:

One SPI Instruction

CS

SCK

SI

MSB

LSB MSB

LSB

op code 14 hex

Forꢀ readꢀ instructions,ꢀ theꢀ mostꢀ signiﬁcantꢀ bitꢀ ofꢀ theꢀ

requested data word appears at the SO pin after the last

opꢀcodeꢀbitꢀisꢀclockedꢀintoꢀtheꢀdecoder,ꢀatꢀtheꢀnextꢀfall-

ingꢀSCKꢀedge.ꢀꢀAsꢀinꢀwriteꢀinstructions,ꢀtheꢀdataꢀﬁeldꢀ

bit-length varies with read instruction type.

data field 0232 hex

ie: Load channel 1 control register with 0232 hex

Figure 2. SPI Instruction Format

Channel-speciﬁcꢀinstructionsꢀuseꢀtheꢀupperꢀfourꢀbitsꢀtoꢀ

specify an ARINC 429 receiver channel, 1-8 hex. The

Table 2. DeﬁnedꢀInstructions

ARINC OP CODE

DATA

FIELD

Description

Channel

Hex

X

0h

None

Instruction not implemented. No operation.

Loadꢀlabelꢀvaluesꢀtoꢀlabelꢀmemory.ꢀTheꢀdataꢀﬁeldꢀconsistsꢀofꢀ16,ꢀ8-bitꢀlabels.ꢀ

1h - 8h

1h

128 bits If fewer than 16 labels are needed for the application, the memory must be

padded with redundant (duplicate) label values.

1h - 8h

2h

3h

128 bits Read the contents of the label memory for this channel.

Read an ARINC word from the receive FIFO for this channel. If the FIFO is

32 bits

empty all zeros will be read.

1h - 8h

4h

5h

6h

7h

16 bits

None

Loadꢀtheꢀspeciﬁedꢀchannel’sꢀControlꢀRegisterꢀandꢀclearꢀthatꢀchannel’sꢀFIFO.

Readꢀtheꢀspeciﬁedꢀchannel’sꢀControlꢀRegister.

Read the Status Register.

1h - 8h

X

Master Reset (All channels).

Load the Transmit Register (High-speed data rate). This can also be used as

aꢀtestꢀwordꢀforꢀeachꢀreceiverꢀ(Loopbackꢀself-test).ꢀ

X

8h

32 bits

Load the Transmit Register (Low-speed data rate). This can also be used

asꢀaꢀtestꢀwordꢀforꢀeachꢀreceiverꢀ(Loopbackꢀself-test).ꢀ

X

9h

32 bits

None

Ah - Fh

Instruction not implemented. No operation.

HOLT INTEGRATED CIRCUITS

4

HI-3596, HI-3597, HI-3598, HI-3599

FUNCTIONAL DESCRIPTION

Status Register

Control Word Register

The HI-359x devices have a single 16-bit Status Reg-

ister which is read to determine status for the eight

received data FIFOs. The Status Register is read using

SPI instruction n6 hex. Table 4 summarizes the Status

Register bits functions.

Each HI-359x receive channel is assigned a 16-bit

Controlꢀ Registerꢀ whichꢀ conﬁguresꢀ thatꢀ receiver.ꢀ Con-

trol Register bits CR15 - CR0 are loaded from a 16-bit

data value appended to SPI instruction n4 hex, where

“n”ꢀisꢀtheꢀchannelꢀnumberꢀ1-8ꢀhex.ꢀWritingꢀtoꢀtheꢀCon-

trol Register also clears the data FIFO for that channel.

The Control Register contents may be read using SPI

instruction n5 hex. Table 3 summarizes the Control Reg-

ister bits functions.

Table 4. Status Register Bits Functions

CR Bit Function

State Description

Receiver 1 FIFO contains valid data.

Table 3. Control Register Bits Functions

Resets to Zero when all data has been

read.ꢀꢀFLAGꢀꢀpinꢀreﬂectsꢀtheꢀstateꢀofꢀ

thisꢀbitꢀwhenꢀCR1=”0”

0

SR0

(LSB)

Receiver 1

FIFO Empty

CR Bit Function

State Description

1

Receiver 1 FIFO is empty

Data rate = ACLK/10 (ARINC 429

0

1

0

1

Receiver

CR0

High-Speed)

0

1

Receiver 2 FIFO contains valid data.

Receiver 2 FIFO is empty

Data Rate

(LSB)

Receiver 2

FIFO Empty

SR1

Data rate = ACLK/80 (ARINC 429

Low-Speed)

Select

Receiver 3

to

Receiver 7

FIFO Empty

:

FLAG goes high when receive FIFO is

not empty (Contains at least one word)

SR2

to

SR6

RFLAG

CR1

Deﬁnition

FLAG goes high when receive FIFO

is full

0

1

Receiver 8 FIFO contains valid data.

Receiver 8 FIFO is empty

Receiver 8

FIFO Empty

SR7

SR8

SR9

Enable

0

1

0

Label recognition disabled

Label recognition enabled

Normal Operation

CR2

CR3

Label

Recognition

Receiver 1 FIFO not full. FLAG pin

reﬂectsꢀtheꢀstateꢀofꢀthisꢀbitꢀwhenꢀ

CR1=”1”

0

1

Receiver 1

FIFO Full

Reset

Receiver

Reset this receiver (Clear receiver

logic and FIFO). The receive channel

is disabled if CR3 is left high

Receiver 1 FIFO full. To avoid data

loss, the FIFO must be read within one

ARINC word period.

1

0

1

Receiverꢀparityꢀcheckꢀdisabled

Receiver

ParityꢀCheckꢀ

Enable

0

1

Receiver 2 FIFO not full.

Receiver 2 FIFO full.

Receiver 2

FIFO Full

CR4

CR5

CR6

Receiverꢀoddꢀparityꢀcheckꢀenabled

Receiver 3

to

Receiver 7

FIFO Full

:

Receiver’sꢀinputsꢀareꢀconnectedꢀtoꢀtheꢀ

Transmit Register serial data output.

SR10

to

SR14

0

Self-Test

(Loopback)

1

0

Normal operation

0

1

Receiver 8 FIFO not full.

Receiver 8 FIFO full.

Receiver Decoder Disabled

SR15

(MSB)

Receiver 8

FIFO Full

Receiver

Decoder

ARINC bits 10 and 9 must match CR7

and CR8

1

-

If receiver decoder is enabled, the

ARINC bit 10 must match this bit

CR7

CR8

-

If receiver decoder is enabled, the

ARINC bit 9 must match this bit

-

0

1

Label bit order reversed (See Table 5)

ARINC

Label Bit

Order

CR9

Label bit order same as received (See

Table 5)

CR10

to

CR15

(MSB)

Controlꢀregisterꢀreadꢀreturnsꢀ“0”ꢀforꢀ

these bits

Not Used

X

HOLT INTEGRATED CIRCUITS

5

HI-3596, HI-3597, HI-3598, HI-3599

ARINC 429 Data Format

DIFFERENTIAL

AMPLIFIERS

COMPARATORS

VDD

RINA-40

Control Register bit CR9 controls how individual bits in

the received ARINC word are mapped to the HI-359x

SPI data word during data read operations. Table 5

describes this mapping.

ONE

RINA

NULL

ZERO

GND

VDD

Table 5. SPI / ARINC bit-mapping

RINB

RINB-40

SPI / ARINC bit-mapping

GND

SPI Order

1

2 - 22 23 24 25 26 27 28 29 30 31 32

9 1 2 3 4 5 6 7 8

ARINC bit 32 31 - 11 10

Figure 3. ARINC Receiver Input

The HI-359x family guarantees recognition of these lev-

els with a common mode Voltage with respect to GND

less than ±30V for the worst case condition (3.15V sup-

ply and 13V signal level).

CR9 = 0

Data

ARINC bit 32 31 - 11 10

9

8

7

6

5

4

3

2

1

The tolerances in the design guarantee detection of

the above levels, so the actual acceptance ranges are

slightly larger. If the ARINC signal is out of the actual

acceptance ranges, including the nulls, the chip rejects

the data.

CR9 = 1

Data

Receiver Logic Operation

Figureꢀ4ꢀisꢀaꢀblockꢀdiagramꢀshowingꢀtheꢀlogicꢀforꢀeachꢀ

receiver.

ARINC 429 Receiver

ARINC Bus Interface

Bit Timing

Figure 3 shows the input circuit for each on-chip ARINC

429ꢀlineꢀreceiver.ꢀꢀTheꢀARINCꢀ429ꢀspeciﬁcationꢀrequiresꢀ

detection levels summarized in Table 6.

TheꢀARINCꢀ429ꢀspeciﬁcationꢀdeﬁnesꢀtimingꢀtolerancesꢀ

for received data according to Table 7.

Table 7. ARINC 429 Receiver Timing Tolerances

HIGH SPEED

100Kbps ± 1%

1.5ꢀ±ꢀ0.5μs

5μsꢀ±ꢀ5%

LOW SPEED

12K - 14.5Kbps

10ꢀ±ꢀ5μs

Table 6. ARINC 429 Detection Levels

Bit Rate

STATE DIFFERENTIAL VOLTAGE

Pulse Rise Time

Pulse Fall Time

Pulse Width

ONE

NULL

ZERO

+6.5 Volts to +13 Volts

+2.5 Volts to -2.5 Volts

-6.5 Volts to -13 Volts

10ꢀ±ꢀ5μs

34.5ꢀtoꢀ41.7μs

HOLT INTEGRATED CIRCUITS

6

HI-3596, HI-3597, HI-3598, HI-3599

SCK

CS

SI

SPI INTERFACE

SO

4 words x 32-bit

FIFO

FLAG

FIFO

LOAD

CONTROL

LABEL /

DECODE

COMPARE

CONTROL BITS

CR2, CR6-8

/

16-label

Memory

BIT

COUNTER

AND

END OF

SEQUENCE

32ND

BIT

ACLK

DATA

PARITY

CHECK

32-BIT SHIFT REGISTER

BIT CLOCK

EOS

WORD GAP

TIMER

WORD GAP

ONES

SHIFT REGISTER

BIT CLOCK

END

START

SEQUENCE

CONTROL

NULL

SHIFT REGISTER

ERROR

CLOCK

ZEROS

ERROR

DETECTION

Figure 4. ReceiverꢀBlockꢀDiagram

The HI-359x family accept signals within these toler-

ances and rejects signals outside these tolerances.

Receiver logic achieves this as described below:

registersꢀclockꢀlowꢀbitsꢀifꢀtheꢀdifferentialꢀinputꢀvolt-

ageꢀisꢀbetweenꢀdeﬁnedꢀstateꢀvoltageꢀbands.ꢀ

Valid data bits require at least three consecutive

One or Zero samples (three high bits) in the upper

half of the Ones or Zeros sampling shift register, and

at least three consecutive Null samples (three high

bits) in the lower half of the Null sampling shift regis-

ter within the data bit interval.

1. Anꢀaccurateꢀ1MHzꢀclockꢀsourceꢀisꢀrequiredꢀtoꢀvali-

date the receive signal timing. Less than 0.1% error

is recommended.

2. The receiver uses three separate 10-bit sampling

shift registers for Ones detection, Zeros detection

and Null detection. When the input signal is within

theꢀdifferentialꢀvoltageꢀrangeꢀforꢀanyꢀshiftꢀregister’sꢀ

stateꢀ(OneꢀZeroꢀorꢀNull)ꢀsamplingꢀclocksꢀaꢀhighꢀbitꢀ

into that register. When the receive signal is outside

theꢀ differentialꢀ voltageꢀ rangeꢀ deﬁnedꢀ forꢀ anyꢀ shiftꢀ

register,ꢀaꢀlowꢀbitꢀisꢀclocked.ꢀOnlyꢀoneꢀshiftꢀregisterꢀ

canꢀclockꢀaꢀhighꢀbitꢀforꢀanyꢀgivenꢀsample.ꢀAllꢀthreeꢀ

A word gap Null requires at least three consecutive

Null samples (three high bits) in the upper half of the

Null sampling shift register and at least three con-

secutive Null samples (three high bits) in the lower

half of the Null sampling shift register. This guaran-

tees the minimum pulse width.

HOLT INTEGRATED CIRCUITS

7

HI-3596, HI-3597, HI-3598, HI-3599

3. To validate the receive data bit rate, each bit must

Table 9. FIFO Loading Control

follow its preceding bit by not less than 8 samples

and not more than 12 samples. With exactly 1MHz

inputꢀclockꢀfrequency,ꢀtheꢀacceptableꢀdataꢀbitꢀratesꢀ

are shown in Table 8.

ARINC word

bits 10, 9

match CR7, 8

matches

Enabled

label

CR2

CR6

FIFO

Table 8. Acceptable Data Bit Rates at 1MHz Input

0

1

0

1

X

No

Yes

X

0

1

X

Load FIFO

Ignore Data

Load FIFO

Ignore Data

Load FIFO

Ignore Data

Load FIFO

ClockꢀFrequency

HIGH SPEED LOW SPEED

X

Data Bit Rate Min

Data Bit Rate Max

83Kbps

10.4Kbps

15.6Kbps

No

Yes

No

Yes

No

Yes

125Kbps

X

Yes

No

Yes

4. Following the last data bit of a valid reception, the

Word Gap timer samples the Null shift register every

10ꢀinputꢀclocksꢀ(everyꢀ80ꢀclocksꢀforꢀlowꢀspeed).ꢀIfꢀ

a Null is present, the Word Gap counter is incre-

mented. A Word Gap count of 3 enables the next

reception.

Once a valid ARINC word is loaded into the FIFO, the

EOSꢀ signalꢀ clocksꢀ theꢀ Dataꢀ Readyꢀ ﬂip-ﬂopꢀ toꢀ aꢀ “1”,ꢀ

andꢀtheꢀcorrespondingꢀchannel’sꢀStatusꢀRegisterꢀFIFOꢀ

Emptyꢀ bitꢀ (SR0-ꢀ SR7)ꢀ goesꢀ toꢀ aꢀ “0”.ꢀ Theꢀ channel’sꢀ

Empty bit remains low until the corresponding Receive

FIFO is empty. Each received ARINC word is retrieved

via the SPI interface using SPI instruction n3 hex where

“n”ꢀisꢀtheꢀchannelꢀnumberꢀ1-8ꢀhex.

Receiver Parity

IfꢀenabledꢀbyꢀsettingꢀControlꢀRegisterꢀCR4ꢀbitꢀtoꢀ“1”,ꢀtheꢀ

receiver parity circuit counts Ones received, including

theꢀparityꢀbit.ꢀꢀIfꢀtheꢀresultꢀisꢀodd,ꢀthenꢀaꢀ“0”ꢀappearsꢀinꢀ

the 32^ndbit.

SettingꢀControlꢀRegisterꢀCR4ꢀbitꢀtoꢀ“0”ꢀdisablesꢀparityꢀ

checkingꢀandꢀallꢀ32ꢀbitsꢀareꢀtreatedꢀasꢀdata.

Upꢀtoꢀ4ꢀARINCꢀwordsꢀmayꢀbeꢀheldꢀinꢀeachꢀchannel’sꢀ

Receive FIFO. The Status Register FIFO Full bit (SR8

-ꢀ SR15)ꢀ goesꢀ highꢀ whenꢀ theꢀ correspondingꢀ channel’sꢀ

Receiveꢀ FIFOꢀ isꢀ full.ꢀ Failureꢀ toꢀ ofﬂoadꢀ aꢀ fullꢀ Receiveꢀ

FIFO causes additional received valid ARINC words to

overwrite the last received word.

Retrieving Data

Once 32 valid bits are recognized, the receiver logic

generates an End of Sequence (EOS). Depending on

the state of Control Register bits CR2, CR6, CR7 and

CR8,ꢀtheꢀreceivedꢀ32-bitꢀARINCꢀwordꢀisꢀthenꢀcheckedꢀ

for correct decoding and label match before it is loaded

into the 4 x 32 Receive FIFO. ARINC words that do not

match required 9th and 10th ARINC bit and do not have

a label match are ignored and are not loaded into the

Receive FIFO. Table 9 describes this operation.

Label Recognition

Theꢀuserꢀloadsꢀtheꢀ16ꢀbyteꢀlabelꢀlook-upꢀtableꢀtoꢀspec-

ify which 8-bit incoming ARINC labels are captured by

the receiver, and which are discarded. If fewer than 16

labels are required, spare label memory locations must

beꢀﬁlledꢀwithꢀduplicateꢀcopiesꢀofꢀanyꢀvalidꢀlabel.ꢀAfterꢀtheꢀ

look-upꢀtableꢀisꢀinitialized,ꢀsetꢀchannelꢀControlꢀRegisterꢀ

bit CR2 to enable label recognition for that channel.

If label recognition is enabled, the receiver compares

theꢀlabelꢀinꢀeachꢀnewꢀARINCꢀwordꢀagainstꢀtheꢀchannel’sꢀ

storedꢀlabelꢀlook-upꢀtable.ꢀꢀIfꢀaꢀlabelꢀmatchꢀisꢀfound,ꢀtheꢀ

received word is processed. If no match occurs, the new

ARINC word is discarded and no indicators of received

ARINC data are presented. Note that 00 hex is treated

in the same way as any other label value. Label memory

bitꢀsigniﬁcanceꢀisꢀnotꢀchangedꢀbyꢀtheꢀstatusꢀofꢀControlꢀ

RegisterꢀbitꢀCR9.ꢀTheꢀmostꢀsigniﬁcantꢀlabelꢀbitꢀisꢀalwaysꢀ

HOLT INTEGRATED CIRCUITS

8

HI-3596, HI-3597, HI-3598, HI-3599

comparedꢀtoꢀtheꢀﬁrstꢀ(MSB)ꢀbitꢀofꢀeachꢀSPIꢀ8-bitꢀdataꢀ

ﬁeldꢀfromꢀSPIꢀinstructionꢀn1ꢀhex,ꢀwhereꢀ“n”ꢀisꢀtheꢀchan-

Line Receiver Input Pins

The HI-3598 has two sets of Line Receiver input pins,

RINA/B and RINA/B-40. Only one pair may be used

to connect to the ARINC 429 bus. THE RINA/B pins

may be connected directly to the ARINC 429 bus. The

RINA/B-40ꢀpinsꢀrequireꢀanꢀexternalꢀ40KΩꢀresistorꢀtoꢀbeꢀ

added in series with each ARINC input without affect-

ing the ARINC input thresholds. This option is especially

useful in applications where lightning protection circuitry

is also required.

nel number 1-8 hex.

IfꢀaꢀchannelꢀControlꢀRegisterꢀCR2ꢀbitꢀequalsꢀ”0,”ꢀtheꢀcor-

responding receiver recognizes all label values as valid,

as shown in Table 9.

Reading the Label Memory

Theꢀcontentsꢀofꢀeachꢀchannel’sꢀLabelꢀMemoryꢀmayꢀbeꢀ

read via the SPI interface using instruction n2 hex where

“n”ꢀequalsꢀtheꢀchannelꢀnumberꢀ1-8ꢀhex,ꢀasꢀdescribedꢀinꢀ

Table 2.

When using the RINA/B-40 pins, each side of the ARINC

busꢀmustꢀbeꢀconnectedꢀthroughꢀaꢀ40KΩꢀseriesꢀresistorꢀ

in order for the chip to detect the correct ARINC levels.

The typical 10V differential signal is translated and input

to a window comparator and latch. The comparator lev-

elsꢀareꢀsetꢀsoꢀthatꢀwithꢀtheꢀexternalꢀ40KΩꢀresistors,ꢀtheyꢀ

are just below the standard 6.5V minimum ARINC data

threshold and just above the standard 2.5V maximum

ARINC null threshold.

Digital Transmit Function

The Transmit Register can be used as a digital transmit-

ter by connecting the TX1 and TX0 pins to an external

ARINC 429 line driver such as the HI-8570 or HI-8571

(except HI-3599).

When using HI-3596, HI-3597 or HI-3599, only one set

of ARINC 429 receive inputs are provided for each chan-

nel. The standard HI-3596, HI-3597 and HI-3599 use the

direct-connection RINA / RINB pins. The HI-3596-40,

HI-3597-40 and HI-3599-40 devices use the RINA-40 /

RINB-40ꢀpinsꢀandꢀrequireꢀexternalꢀ40KΩꢀseriesꢀresis-

tors. See the Ordering Information table for complete

part number options.

Loopback Self-Test

The HI-359x devices may use the Transmit Register

toꢀexecuteꢀuser-deﬁnedꢀself-testꢀsequencesꢀ(loopbackꢀ

test) for each receiver. This feature may be individually

enabled for each receiver by resetting Control Register

CR5ꢀbitꢀtoꢀ“0”.ꢀꢀAꢀ32-bitꢀtestꢀwordꢀisꢀloadedꢀtoꢀtheꢀTrans-

mit Register using SPI instructions n8 hex (for ARINC

429 high-speed data rate) or n9 hex (for ARINC 429 low

speed). Upon completion of the instruction, the word is

shifted out of the register and routed to all receivers.

If self-test mode is enabled and the receive channel

is set to the correct speed, each channel will receive

the test word as if it came from an external ARINC 429

bus.ꢀIfꢀloopbackꢀisꢀnotꢀenabled,ꢀtheꢀchannelꢀignoresꢀtheꢀ

self-test word and continues to respond to the external

ARINC 429 bus (Note: In the case of HI-3597, RIN1A

and RIN1B pins are not available). In all cases, the serial

test word may be observed at the TX1 and TX0 pins

(except HI-3599), as shown in Table 10.

Please refer to the Holt AN-300 Application Note for

additional information and recommendations on light-

ning protection of Holt line drivers and line receivers.

Master Reset (MR)

Assertion of Master Reset (MR) causes immediate ter-

mination of data reception. The eight Receive FIFOs

areꢀcleared.ꢀStatusꢀRegisterꢀFIFOꢀﬂagsꢀandꢀFIFOꢀstatusꢀ

output signals are also cleared. Master Reset does not

affect the eight channel Control Registers. Master Reset

may be asserted using the MR input pin (HI-3596 and

HI-3598 only) or by executing SPI instruction n7 hex.

NOTE:ꢀTheꢀﬁrstꢀbitꢀshiftedꢀintoꢀtheꢀSelfꢀTestꢀregisterꢀwillꢀ

beꢀtheꢀﬁrstꢀbitꢀsentꢀtoꢀtheꢀreceiversꢀandꢀtheꢀTX1ꢀandꢀTX0ꢀ

pins. In ARINC 429 protocol, this bit is the LSB.

An individual receive channel can be reset by setting

itsꢀcorrespondingꢀControlꢀRegisterꢀCR3ꢀbitꢀtoꢀ“1”.ꢀThisꢀ

clearsꢀ theꢀ channel’sꢀ receiverꢀ logicꢀ andꢀ Receiveꢀ FIFOꢀ

andꢀdisablesꢀtheꢀreceiverꢀuntilꢀCR3ꢀisꢀresetꢀtoꢀ“0”.ꢀForꢀ

applications requiring less than eight channels, unused

receivers should be held in reset by setting the corre-

sponding Control Register CR3 bits.

Table 10. Test Outputs

TX1

0

TX0

0

ARINC 429 State

NULL

1

0

ONE

0

1

ZERO

HOLT INTEGRATED CIRCUITS

9

HI-3596, HI-3597, HI-3598, HI-3599

TIMING DIAGRAMS

SERIAL INPUT TIMING DIAGRAM

t _CPH

CS

t_CHH

t_CES

t _SCKF

t _CEH

SCK

t_DS

t_DH

t _SCKR

SI

MSB

LSB

SERIAL OUTPUT TIMING DIAGRAM

t _CPH

CS

t_SCKH

t_SCKL

SCK

t _CHZ

t _DV

MSB

SO

LSB

Hi Impedance

RECEIVER OPERATION

BIT 31

BIT 32

ARINC DATA

FLAG

t_RFLG

t_SPIF

t_RXR

CS

SCK

SI

SPI INSTRUCTION n3 hex

SO

ARINC

WORD

Figure 5. Timing Diagrams

HOLT INTEGRATED CIRCUITS

10

HI-3596, HI-3597, HI-3598, HI-3599

ABSOLUTE MAXIMUM RATINGS

Supply Voltages V_DD...................................................... -0.3 to +7.0V Power dissipation at 25^oC

PlasticꢀQuadꢀFlatꢀPackꢀ..........................ꢀ1.5ꢀW,ꢀderateꢀ10mW/^oC

Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ........... -29V to +29V DC Current Drain per pin ........................................................ ±10mA

Storage Temperature Range ................................... -65^oC to +150^oC

Voltage at any other pin ......................................... -0.3V to V_DD+0.3V

Solder temperature (Leads) ............................ 280^oC for 10 seconds

Operating Temperature Range (Industrial) ................ -40°C to +85°C

(Extended Temp) .............. -55^oC to +125^oC

(Package)ꢀ....................................................ꢀ220^oC

NOTE: Stressesꢀaboveꢀthoseꢀlistedꢀunderꢀ“AbsoluteꢀMaximumꢀRatings”ꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀ

Functionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀtheꢀspeciﬁcationsꢀisꢀnotꢀ

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Table 11. DC Electrical Characteristics

V_DD= 3.3V or 5.0V, GND = 0V, T_A= Operating Temperature Range (unless otherwise stated)

Limits

Parameters

Symbol

Test Conditions

Unit

Min

Typ

Max

ARINC INPUTS

-

Pins RINA, RINB, RINA-40 (with external 40KΩ), RINB-40 (with external 40KΩ)

Differential Input Voltage

ONE

ZERO

NULL

V_IH

V_IL

Common mode voltages

less than ±30V with

respect to GND

6.5

-13.0

-2.5

10.0

-10.0

0

13.0

-6.5

2.5

V

(RIN1A to RIN1B, RIN2A

to RIN2B, etc.)

V_NUL

Input Resistance

Differential

To GND

To V_DD

R_I

R_G

R_H

-

140

100

-

kΩ

Input Current

InputꢀSink

I_IH

I_IL

-

200

-

μA

Input Source

-450

Inpit Capacitance

Differential

To GND

To V_DD

C_I

C_G

C_H

(RINA to RINB)

-

20

pF

(Guaranteed but not

tested)

LOGIC INPUTS

Input Voltage

Input Voltage HI

Input Voltage LO

V_IH

V_IL

70% V_DD

-

V

30% V_DD

I_IH

I_IL

-

1.5

-

μA

InputꢀSink

-1.5

250

Input Source

Input Current

I_PD

600

Pull-down Current (MR, SI, SCK,

ACLK pins)

Pull-up Current (CS)

I_PU

-600

-

-250

μA

LOGIC OUTPUTS

Logicꢀ“1”ꢀOutputꢀVoltage

Logicꢀ“0”ꢀOutputꢀVoltage

V_OH

V_OL

I_OHꢀ=ꢀ-100μA

90% V_DD

-

V

Output Voltage

I_OL= 1.0mA

10% V_DD

HOLT INTEGRATED CIRCUITS

11

HI-3596, HI-3597, HI-3598, HI-3599

Limits

Typ

Parameters

Symbol

Test Conditions

Unit

Min

Max

OutputꢀSink

I_OH

I_OL

V_OUT= 0.4V

1.6

-

mA

Output Current

Output Source

V_OUT= V_DD-0.4V

-1.0

(All outputs and Bi-

directional pins)

Output Capacitance

C_O

V_DD

I_DD

-

3.15

-

15

-

pF

V

OPERATING VOLTAGE RANGE

5.25

7.0

OPERATING SUPPLY CURRENT

2.5

mA

Table 12. AC electrical characteristics

VDD = 3.3V or 5.0V, GND = 0V, T_A= Operating Temperature Range and f_clk=1MHz ±0.1% with 60/40 duty cycle

Limits

Typ

Parameters

Symbol

Units

Min

Max

SPI INTERFACE TIMING

SCKꢀclockꢀPeriod

t_CYC

t_CHH

t_CES

t_CEH

t_CPH

t_DS

130

25

10

30

10

30

-

ns

CS active after last SCK rising edge

CSꢀsetupꢀtimeꢀtoꢀﬁrstꢀSCKꢀrisingꢀedge

CS hold time after last SCK falling edge

CS inactive between SPI instructions

SPI SI Data set-up time to SCK rising edge

SPI SI Data hold time after SCK rising edge

SCK rise time

-

t_DH

-

t_SCKR

t_SCKF

t_SCKH

t_SCKL

t_DV

10

-

SCK fall time

-

SCK high time

45

25

-

SCK low time

-

SO valid after SCK falling edge

SO high-impedance after SCK falling edge

65

t_CHZ

-

RECEIVER TIMING

Delay - Last bit of received ARINC word to FLAG (Full or Empty) - Hi Speed

Delay - Last bit of received ARINC word to FLAG (Full or Empty) - Lo Speed

t_RFLG

-

16

μs

126

Received data available to SPI interface. FLAG to CS active

SPI receiver read

t_RXR

t_SPIF

0

-

ns

85

HOLT INTEGRATED CIRCUITS

12

HI-3596, HI-3597, HI-3598, HI-3599

HEAT SINK - CHIP SCALE PACKAGE (QFN) ONLY

TheꢀHI-3596PCx,ꢀHI-3598PCx,ꢀandꢀHI3599PCxꢀuseꢀ44-pinꢀorꢀ64-pinꢀplasticꢀchip-scaleꢀ(QFN)ꢀpackages.ꢀTheseꢀpack-

agesꢀhaveꢀaꢀmetalꢀheatꢀsinkꢀpadꢀonꢀtheꢀbottomꢀsurfaceꢀthatꢀisꢀelectricallyꢀconnectedꢀtoꢀtheꢀdie.ꢀꢀForꢀtheseꢀreceivers,ꢀ

smallꢀsizeꢀisꢀtheꢀprimaryꢀadvantageꢀofꢀthisꢀpackageꢀstyle.ꢀHeatꢀsinkingꢀprovidesꢀlittleꢀbeneﬁtꢀbecauseꢀpowerꢀdissipationꢀ

isꢀlow.ꢀIfꢀconnected,ꢀtheꢀbottomꢀheatꢀsinkꢀpadꢀshouldꢀbeꢀconnectedꢀtoꢀVDD.

DoꢀnotꢀconnectꢀheatꢀsinkꢀpadꢀtoꢀGND.

ADDITIONAL PIN / PACKAGE CONFIGURATIONS

HI-3596PCx

HI-3596PCx-40

ACLK -

1

2

3

4

5

6

7

8

9

33 -

ACLK -

1

2

3

4

5

6

7

8

9

33 -

SCK -

32 - RIN8A

31 -

__

SCK -

32 - RIN8A-40

31 -

__

CS -

SI -

CS -

SI -

30 - RIN7B

29 - RIN7A

28 - RIN6B

27 - RIN6A

26 - RIN5B

25 - RIN5A

24 -

30 - RIN7B-40

29 - RIN7A-40

28 - RIN6B-40

27 - RIN6A-40

26 - RIN5B-40

25 - RIN5A-40

24 -

SO -

HI-3596PCI

HI-3596PCT

HI-3596PCI-40

HI-3596PCT-40

MR -

TX1 -

TX0 -

RIN1A -

TX1 -

TX0 -

RIN1A-40 -

RIN1B - 10

- 11

RIN1B-40 - 10

- 11

23 -

44-Pin Plastic 7mm x 7mm

Chip-Scale Package (QFN)

44-Pin Plastic 7mm x 7mm

Chip-Scale Package (QFN)

HI-3598PCx

HI-3597PSx-40

ACLK - 1

SCK - 2

CS - 3

SI - 4

SO - 5

24 - VDD

23 - FLAG

- 1

- 2

48 - RIN8A-40

47 - RIN8A

46 - RIN7B

45 - RIN7B-40

44 - RIN7A-40

43 - RIN7A

42 -

22 - RIN8B-40

21 - RIN8A-40

20 - RIN7B-40

19 - RIN7A-40

18 - RIN6B-40

17 - RIN6A-40

16 - RIN5B-40

15 - RIN5A-40

14 - RIN4B-40

13 - RIN4A-40

HI-3597

PSI-40

&

HI-3597

PST-40

ACLK - 3

SCK - 4

CS - 5

TX1 - 6

TX0 - 7

RIN2A-40 - 8

RIN2B-40 - 9

RIN3A-40 - 10

RIN3B-40 - 11

GND - 12

SI - 6

SO - 7

HI-3598PCI

HI-3598PCT

MR - 8

41 - RIN6B

40 - RIN6B-40

39 -

TX1 - 9

TX0 - 10

RIN1A - 11

RIN1A-40 - 12

RIN1B-40 - 13

RIN1B - 14

- 15

38 - RIN6A-40

37 - RIN6A

36 - RIN5B

35 - RIN5B-40

34 - RIN5A-40

33 - RIN5A

24 - Pin Plastic Small Outline Package (SOIC)

- 16

64-Pin Plastic 9mm x 9mm

Chip-Scale Package (QFN)

HOLT INTEGRATED CIRCUITS

13

HI-3596, HI-3597, HI-3598, HI-3599

HI-3599PCx-40

HI-3599PCx

-

1

2

3

4

5

6

7

8

9

33 -

-

1

2

3

4

5

6

7

8

9

33 -

-

32 -

-

32 -

-

SI -

31 -

-

31 -

30 - RIN7B

29 - RIN7A

28 - RIN6B

27 - RIN6A

26 - RIN5B

25 - RIN5A

24 -

SI -

30 - RIN7B-40

29 - RIN7A-40

28 - RIN6B-40

27 - RIN6A-40

26 - RIN5B-40

25 - RIN5A-40

24 -

SO -

-

SO -

HI-3599PCI

HI-3599PCT

HI-3599PCI-40

HI-3599PCT-40

-

RIN1A -

RIN1B -

RIN1A-40 -

RIN1B-40 -

- 10

- 11

- 10

- 11

23 -

44-Pin Plastic 7mm x 7mm

Chip-Scale Package (QFN)

44-Pin Plastic 7mm x 7mm

Chip-Scale Package (QFN)

HI-3599PSx

HI-3599PSx-40

ACLK - 1

SCK - 2

CS - 3

SI - 4

SO - 5

RIN1A - 6

RIN1B - 7

RIN2A - 8

RIN2B - 9

RIN3A - 10

RIN3B - 11

GND - 12

24 - VDD

ACLK - 1

SCK - 2

CS - 3

SI - 4

SO - 5

24 - VDD

23 - FLAG

22 - RIN8B

21 - RIN8A

20 - RIN7B

19 - RIN7A

18 - RIN6B

17 - RIN6A

16 - RIN5B

15 - RIN5A

14 - RIN4B

13 - RIN4A

22 - RIN8B-40

21 - RIN8A-40

20 - RIN7B-40

19 - RIN7A-40

18 - RIN6B-40

17 - RIN6A-40

16 - RIN5B-40

15 - RIN5A-40

14 - RIN4B-40

13 - RIN4A-40

HI-3599

PSI

HI-3599

PSI-40

&

HI-3599

PST-40

RIN1A-40 - 6

RIN1B-40 - 7

RIN2A-40 - 8

RIN2B-40 - 9

RIN3A-40 - 10

RIN3B-40 - 11

GND - 12

&

HI-3599

PST

24 - Pin Plastic Small Outline Package (SOIC)

HOLT INTEGRATED CIRCUITS

14

HI-3596, HI-3597, HI-3598, HI-3599

ORDERING INFORMATION (HI-3598 all pins)

HI - 3598 xx x x

PART NUMBER LEAD FINISH

Blank

Tin / Lead (Sn / Pb) Solder

100% Matte Tin (Pb-free, RoHS compliant)

F

PART NUMBER TEMPERATURE RANGE

FLOW BURN IN

I

-40^oC to +85^oC

-55^oC to +125^oC

I

No

T

PART NUMBER PACKAGE DESCRIPTION

PC

PQ

64 PIN PLASTIC CHIP-SCALE PACKAGE, QFN (64PCS)

52 PIN PLASTIC QUAD FLAT PACK, PQFP (52PTQS)

ORDERING INFORMATION (HI-3596¹, HI-3597²& HI-3599)

HI - 359x xx x x - xx

PART NUMBER INPUT RESISTANCE

Blank

140kΩ.ꢀDirectꢀconnectionꢀtoꢀARINCꢀ429ꢀbus

100kΩ.ꢀRequiresꢀexternalꢀ40kΩꢀresistors

-40

PART NUMBER LEAD FINISH

Blank

Tin / Lead (Sn / Pb) Solder

100% Matte Tin (Pb-free, RoHS compliant)

F

PART NUMBER TEMPERATURE RANGE

FLOW BURN IN

I

-40^oC to +85^oC

-55^oC to +125^oC

I

No

T

PART NUMBER PACKAGE DESCRIPTION

PC

PS

44 PIN PLASTIC CHIP-SCALE PACKAGE, QFN (44PCS)

24 PIN PLASTIC WIDE SOIC, (24HW)

PART NUMBER

3596¹

DIGITAL TRANSMIT FUNCTION

Yes

No

¹Not available in PSx package.

²Not available in PCx package.

3597²

3599

HOLT INTEGRATED CIRCUITS

15

HI-3596, HI-3597, HI-3598, HI-3599

REVISION HISTORY

Revision

Date

Description of Change

DS3598, Rev. NEW 6/12/08

Initial Release.

Rev. A

Rev. B

Rev. C

5/22/09

ClariﬁedꢀrelationshipꢀbetweenꢀSPIꢀbitꢀorderꢀandꢀARINCꢀ429ꢀbitꢀorder.

Corrected typo on receivers pin nomenclature on page 3. Added and updated Figure

and Table cross-references. Condensed Control and Status Register tables. Corrected

minorꢀtypos.ꢀClariﬁedꢀcertainꢀfunctionalꢀdescriptions.ꢀ

11/23/09

Added HI3596 & HI-3597 variants to datasheet.

01/18/12 Correct typo in Table 5. Change CR11 to CR9

HOLT INTEGRATED CIRCUITS

16

HI-3596, HI-3597, HI-3598, HI-3599

PACKAGE DIMENSIONS

52-PIN PLASTIC QUAD FLAT PACK (PQFP)

inches (millimeters)

Package Type: 52PTQS

.0256

(.65)

BSC

.520

(13.2)

.394

(10.0)

BSC SQ

.015 ± .003

(.375 ± .075)

.035 ± .006

(.88 ± .15)

.063

(1.6)

typ

.008

(.20)

min

See Detail A

.005

(.13)

R min

.063

(1.6)

MAX.

.055 ± .002

(1.4 ± .05)

0°

7°

.005

(.13)

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

R min

DETAIL A

inches (millimeters)

64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)

Package Type: 64PCS

Heat sink pad on bottom of package.

Heat sink must be left floating or connected to V_DD

DO NOT connect to GND.

.

.354

BSC

.281 ± .006

(7.15 ± .15)

(9.00)

.0197

(0.50)

BSC

typ

.354

(9.00)

.281 ± .006

(7.15 ± .15)

BSC

TopView

Bottom

View

.010

(0.25)

.016 ± .004

(0.40 ± .10)

.008

(0.20)

typ

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

.039

(1.00)

max

HOLT INTEGRATED CIRCUITS

17

HI-3596, HI-3597, HI-3598, HI-3599

inches (millimeters)

24-PIN PLASTIC SMALL OUTLINE (SOIC) - WB

(Wide Body)

Package Type: 24HW

.606 ± .004

(15.392 ± .102)

.0105 ± .0015

(.2667 ± .038)

.294 ± .002

.407 ± .013

(7.468 ± .051)

(10.325 ± .32)

See Detail A

.0165 ± .0035

(.419 ± .089)

.095 ± .005

(2.413 ± .127)

0° to 8°

.050

BSC

(1.27)

.033 ± .017

(.838 ± .43)

.0075 ± .0035

(.191 ± .089)

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

Detail A

inches (millimeters)

44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)

Package Type: 44PCS

.276

BSC

.203 ± .006

(5.15 ± .15)

(7.00)

.020

(0.50)

BSC

typ

TopView

Bottom

View

.276

(7.00)

.203 ± .006

(5.15 ± .15)

BSC

.010

(0.25)

.016 ± .002

(0.40 ± .05)

Heat sink pad on bottom of package.

Heat sink must be left floating or

.039

(1.00)

.008

(0.2)

max

typ

connected to V_DD

.

DO NOT connect to GND.

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

HOLT INTEGRATED CIRCUITS

18

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