C8051F300 参数 Datasheet PDF下载

C8051F300/1/2/3/4/5

13.5.4. Slave Transmitter Mode

Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH

= 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a

slave address and direction bit (READ in this case) is received. Software responds to the received slave

address with an ACK, or ignores the received slave address with a NACK. If the received address is

ignored, slave interrupts will be inhibited until the next START is detected. If the received slave address is

acknowledged, software should write data to SMB0DAT to force the SMBus into Slave Transmitter Mode.

The switch from Slave Receiver to Slave Transmitter requires software management. Software should per-

form the steps outlined below only when a valid slave address is received (indicated by the label “RX-to-TX

Steps” in Figure 13.8).

Step 1.

Step 2.

Step 3.

Step 4.

Step 5.

Step 6.

Step 7.

Set ACK to ‘1’.

Write outgoing data to SMB0DAT.

Check SMB0DAT.7; if ‘1’, do not perform steps 4, 6 or 7.

Set STO to ‘1’.

Clear SI to ‘0’.

Poll for TXMODE => ‘1’.

Clear STO to ‘0’ (must be done before the next ACK cycle).

The interface enters Slave Transmitter Mode and transmits one or more bytes of data (the above steps are

only required before the first byte of the transfer). After each byte is transmitted, the master sends an

acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If

the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error

condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter

Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will

switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt.

any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur

after

the

ACK cycle in this mode.

Perform RX-to-TX

Steps Here

Interrupt

S

SLA

R

A

Data Byte

A

Data Byte

N

P

Interrupt

Received by SMBus

Interface

Transmitted by

SMBus Interface

Interrupt

Interrupt

S = START

P = STOP

N = NACK

W = WRITE

SLA = Slave Address

Figure 13.8. Typical Slave Transmitter Sequence

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Rev. 2.6