CY7C1339
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE
1
, CE
2
, CE
3
, ADSP, and ADSC must remain inactive for the
duration of t
ZZREC
after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
Description
Snooze mode
standby current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > V
DD
−
0.2V
ZZ > V
DD
−
0.2V
ZZ < 0.2V
2t
CYC
Min.
Max.
3
2t
CYC
Unit
mA
ns
ns
Powered by ICminer.com Electronic-Library Service CopyRight 2003
5
ETC [ ETC ]
