CY7C1339
AC Test Loads and Waveforms
OUTPUT
Z
0
=50Ω
R
L
=50Ω
V
L
= 1.5V
3.3V
OUTPUT
5 pF
R=351Ω
INCLUDING
JIG AND
SCOPE
R=317Ω
ALL INPUT PULSES
2.5V
10%
GND
≤
2.5 ns
90%
[10]
90%
10%
≤
2.5ns
(a)
(b)
(c)
Switching Characteristics
Over the Operating Range
[11,12,13]
-166
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CO
t
DOH
t
ADS
t
ADH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Description
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BW[3:0] Set-Up Before CLK Rise
BWE, GW, BW[3:0] Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-Up
Chip Select Hold After CLK Rise
Clock to High-Z
[12]
Clock to Low-Z
[12]
OE HIGH to Output High-Z
[12, 13]
OE LOW to Output Low-Z
[12, 13]
OE LOW to Output Valid
[12]
0
3.5
0
3.5
0
4.0
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
3.5
0
3.5
0
5.5
Min.
6.0
1.7
1.7
2.0
0.5
3.5
2.0
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
3.5
0
5.5
Max.
Min.
7.5
1.9
1.9
2.5
0.5
4.0
2.0
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
3.5
-133
Max.
Min.
10
3.5
3.5
2.5
0.5
5.5
-100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Input waveform should have a slew rate of 1 V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a) and (b) of AC test loads.
12. t
CHZ
, t
CLZ
, t
EOV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mf from steady-state
voltage.
13. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
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