KS8995X
Pin Number
63
64
65
Pin Name
PMRXD2
PMRXD1
PMRXD0
Type
(1)
Ipd/O
Ipd/O
Ipd/O
Port
5
5
5
Pin Function
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
Micrel
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = packet size
1518/1522 bytes; PU = 1536 bytes.
PHY[5] MII carrier sense/force duplex mode. See
“Register 28.”
PHY[5] MII collision detect/force flow control. See
“Register 18.”
Switch MII transmit enable
Switch MII transmit bit 3
Switch MII transmit bit 2
Switch MII transmit bit 1
Switch MII transmit bit 0
Switch MII transmit error
Switch MII transmit clock. PHY or MAC mode MII.
Digital ground
3.3/2.5V digital V
DD
for digital I/O circuitry.
Switch MII receive clock. PHY or MAC mode MII.
Switch MII receive data valid
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in
full-duplex mode; PU = Switch MII in half-duplex mode.
Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
Switch MII receive bit 0; Strap option: see
“Register 11[1].”
Switch MII collision detect
Switch mode carrier sense
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
PMRXER
PCRS
PCOL
SMTXEN
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMTXER
SMTXC
GNDD
VDDIO
SMRXC
SMRXDV
SMRXD3
SMRXD2
SMRXD1
SMRXD0
SCOL
SCRS
Ipd/O
Ipd/O
Ipd/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
Gnd
P
I/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
5
5
5
Ipu = Input w/internal pull-up
Ipd = Input w/internal pull-down
Ipd/O = Input w/internal pull-down during reset, output pin otherwise
Ipu/O = Input w/internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pull-down
Otri = Output tristated
M9999-120403
10
December 2003
ETC [ ETC ]
