KS8995X
Pin Number
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/internal pull-up
Ipd = Input w/internal pull-down
Ipd/O = Input w/internal pull-down during reset, output pin otherwise
Ipu/O = Input w/internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pull-down
Otri = Output tristated
Micrel
Pin Name
VDDAR
RXP5
RXM5
GNDA
TXM5
TXP5
VDDAT
FXSD5
FXSD4
GNDA
VDDAR
GNDA
VDDAR
GNDA
NC / MUX1
NC / MUX2
PWRDN_N
RESERVE/NC
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC
GNDD
VDDIO
PMRXC
PMRXDV
PMRXD3
Gnd
P
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
O
Gnd
P
O
Ipd/O
Ipd/O
5
5
5
5
5
5
5
5
5
5
Type
(1)
P
I
I
Gnd
O
O
P
I
I
Gnd
P
Gnd
P
Gnd
I
I
Ipu
5
4
5
5
5
5
Port
Pin Function
1.8V analog V
DD
Physical receive signal + (differential)
Physical receive signal - (differential)
Analog ground
Physical transmit signal - (differential)
Physical transmit signal + (differential)
2.5V analog V
DD
Fiber signal detect/factory test pin
Fiber signal detect/factory test pin
Analog ground
1.8V analog V
DD
Analog ground
1.8V analog V
DD
Analog ground
No connect. Factory test pin.
No connect. Factory test pin.
Full-chip power down. Active low.
Reserved pin. No connect.
Digital ground
1.8V digital core V
DD
PHY[5] MII transmit enable
PHY[5] MII transmit bit 3
PHY[5] MII transmit bit 2
PHY[5] MII transmit bit 1
PHY[5] MII transmit bit 0
PHY[5] MII transmit error
PHY[5] MII transmit clock. PHY mode MII.
Digital ground
3.3/2.5V digital V
DD
for digital I/O circuitry
PHY[5] MII receive clock. PHY mode MII.
PHY[5] MII receive data valid
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
December 2003
9
M9999-120403
ETC [ ETC ]
