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产品型号K6X1008C2D-TF55的概述

芯片K6X1008C2D-TF55概述 K6X1008C2D-TF55是由韩国三星电子公司（Samsung Electronics）生产的一款高性能动态随机存取存储器（DRAM）芯片。作为一款广泛应用于计算机、移动设备和嵌入式系统的存储器，K6X1008C2D-TF55在诸多领域得到了高度重视。这款芯片采用了最新的工艺技术和架构设计，具备较高的存取速度和电源效率，能够满足现代电子设备对数据处理和存储的需求。 K6X1008C2D-TF55的主要特点在于其高密度和高性能。它能够支持多种工作模式，并且在设备的低功耗模式下也能保持良好的响应速度和性能可靠性。这使得K6X1008C2D-TF55特别适合于对功耗有严格要求的便携设备和高性能计算任务。芯片K6X1008C2D-TF55的详细参数 K6X1008C2D-TF55具备以下详细参数： - 存储容量：1MB - 技术节点：55nm - ...

产品型号K6X1008C2D-TF55的Datasheet PDF文件预览

K6X1008C2D Family

CMOS SRAM

Document Title

128Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No. History

Draft Data

Remark

0.0

Initial draft

July 15, 2002

Preliminary

0.1

Revised

December 4, 2002

Preliminary

- Deleted 32-TSOP1-0820R Package Type.

- Added Commercial product.

0.2

0.3

1.0

Revised

May 13, 2003

Preliminary

Final

- Added Lead Free 32-SOP-525 Product

Revised

June 21, 2003

- Added Lead Free 32-TSOP1-0820F Product

Finalized

September 16, 2003

- Changed ICC from 10mA to 5mA

- Changed ICC2 from 35mA to 25mA

- Changed ISB from 3mA to 0.4mA

- Changed IDR(industrial) from 15mA to 10mA

- Changed IDR(Automotive) from 25mA to 20mA

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

128Kx8 bit Low Power full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 128K x 8

The K6X1008C2D families are fabricated by SAMSUNG¢s

advanced CMOS process technology. The families support

verious operating temperature ranges and have various pack-

age types for user flexibility of system design. The families

also support low data retention voltage for battery back-up

operation with low data retention current.

· Power Supply Voltage: 4.5~5.5V

· Low Data Retention Voltage: 2V(Min)

· Three state output and TTL Compatible

· Package Type: 32-DIP-600, 32-SOP-525,

32-SOP-525, 32-TSOP1-0820F

PRODUCT FAMILY

Power Dissipation

PKG Type

Operating

Temperature

Product Family

Vcc Range

Speed

Standby

Operating

(ICC2, Max)

(ISB1, Max)

K6X1008C2D-B

K6X1008C2D-F

K6X1008C2D-Q

Commercial(0~70°C)

Industrial(-40~85°C)

Automotive(-40~125°C)

10mA

15mA

25mA

32-DIP-600, 32-SOP-525,

32-SOP-525

4.5~5.5V

55¹⁾/70ns

25mA

32-TSOP1-0820F

32-SOP-525, 32-TSOP1-0820F

1. The parameters are tested with 50pF test load

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Precharge circuit.

VCC

A15

CS2

A13

A16

A14

A12

A11

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

Row

addresses

Row

select

Memory array

A13

CS2

A15

VCC

A16

A14

A12

32-SOP

32-DIP

A11

32-TSOP

Type1-Forward

A10

CS1

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O8

Data

cont

I/O Circuit

I/O1

I/O2

I/O3

VSS

Column select

Data

cont

Column Addresses

Name

Function

CS1, CS2

Chip Select Input

Output Enable Input

Write Enable Input

Data Inputs/Outputs

Address Inputs

Power

CS1

Control

logic

CS2

I/O1~I/O8

A0~A16

Vcc

Vss

Ground

No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

PRODUCT LIST

Commercial Products(0~70°C)

Industrial Products(-40~85°C)

Automotive Products(-40~125°C)

Part Name

Function

Part Name

Function

Part Name

Function

K6X1008C2D-DB55

K6X1008C2D-DB70

K6X1008C2D-GB55

K6X1008C2D-GB70

K6X1008C2D-BB55¹⁾

K6X1008C2D-BB70¹⁾

K6X1008C2D-TB55

K6X1008C2D-TB70

K6X1008C2D-PB55¹⁾

K6X1008C2D-PB70¹⁾

32-DIP, 55ns, LL

K6X1008C2D-DF55

K6X1008C2D-DF70

K6X1008C2D-GF55

K6X1008C2D-GF70

K6X1008C2D-BF55¹⁾

K6X1008C2D-BF70¹⁾

K6X1008C2D-TF55

K6X1008C2D-TF70

K6X1008C2D-PF55¹⁾

K6X1008C2D-PF70¹⁾

32-DIP, 55ns, LL

K6X1008C2D-GQ55

K6X1008C2D-GQ70

K6X1008C2D-TQ55

K6X1008C2D-TQ70

32-SOP, 55ns, L

32-DIP, 70ns, LL

32-SOP, 70ns, L

32-SOP, 55ns, LL

32-SOP, 70ns, LL

32-SOP, 55ns, LL

32-SOP, 70ns, LL

32-TSOP-F, 55ns, LL

32-TSOP-F, 70ns, LL

32-TSOP-F, 55ns, LL

32-TSOP-F, 70ns, LL

32-SOP, 55ns, LL

32-SOP, 70ns, LL

32-SOP, 55ns, LL

32-SOP, 70ns, LL

32-TSOP-F, 55ns, LL

32-TSOP-F, 70ns, LL

32-TSOP-F, 55ns, LL

32-TSOP-F, 70ns, LL

32-TSOP-F, 55ns, L

32-TSOP-F, 70ns, L

1. Lead Free Product

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O

Mode

Deselected

Output Disabled

Read

Power

Standby

Active

X¹⁾

High-Z

Dout

X¹⁾

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

-0.5 to VCC+0.5V(Max. 7.0V)

-0.3 to 7.0

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN,VOUT

VCC

1.0

Storage temperature

TSTG

-65 to 150

°C

0 to 70

K6X1008C2D-B

K6X1008C2D-F

K6X1008C2D-Q

Operating Temperature

-40 to 85

-40 to 125

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

4.5

Typ

Max

5.5

Unit

Supply voltage

Ground

5.0

Vss

Vcc+0.5²⁾

0.8

Input high voltage

Input low voltage

Note:

VIH

2.2

-0.5³⁾

VIL

1. Commercial Product: TA=0 to 70°C, Otherwise specified

Industrial Product: TA=-40 to 85°C, Otherwise specified

Automotive Product: TA=-40 to 125°C, Otherwise specified

2. Overshoot: Vcc+3.0V in case of pulse width£30ns.

3. Undershoot: -3.0V in case of pulse width£30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read

ICC

Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V, CS2³ Vcc-0.2V,

VIN£0.2V or VIN³ VCC-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH,

VIN=VIH or VIL

25 mA

Output low voltage

Output high voltage

Standby Current(TTL)

VOL

VOH

ISB

IOL=2.1mA

0.4

IOH=-1.0mA

2.4

CS1=VIH, CS2=VIL, Other inputs=VIH or VIL

0.4 mA

10 mA

15 mA

25 mA

K6X1008C2D-B

CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or

CS2£0.2V, Other inputs=0~Vcc

Standby Current(CMOS)

ISB1

K6X1008C2D-F

K6X1008C2D-Q

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

Input and output reference voltage:1.5V

Output load(see right): CL=100pF+1TTL

CL=50pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS

(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40~125°C)

Speed Bins

Parameter List

Symbol

Units

55ns

70ns

Min

Max

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

Output Enable to Valid Output

Chip Select to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Write Cycle Time

Read

tLZ

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width

tAW

tWP

tWR

tWHZ

tDW

tDH

Write

Write Recovery Time

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End Write to Output Low-Z

tOW

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

CS1³ Vcc-0.2V¹⁾

Vcc for data retention

VDR

2.0

5.5

K6X1008C2D-B

K6X1008C2D-F

K6X1008C2D-Q

Vcc=3.0V, CS1³ Vcc-0.2V¹⁾

Data retention current

IDR

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

1. CS¹³ Vcc-0.2V, CS2³ VCC-0.2V, or CS2£0.2V

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tRC

Address

tAA

tOH

Data Out

Data Valid

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

CS1

tHZ(1,2)

CS2

tCO2

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tWR(4)

tCW(2)

CS1

tAW

CS2

tCW(2)

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS¹Controlled)

tWC

Address

CS1

tCW(2)

tAS(3)

tWR(4)

tAW

CS2

tWP(1)

tDW

tDH

Data in

Data out

Data Valid

High-Z

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC

Address

CS1

tAS(3)

tCW(2)

tWR(4)

tAW

CS2

tCW(2)

tWP(1)

tDH

tDW

Data Valid

Data in

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,

CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,

tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS¹going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS¹or WE going high tWR2 applied

in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

2.2V

VDR

CS³ VCC - 0.2V

CS1

GND

CS2 controlled

Data Retention Mode

VCC

4.5V

CS2

tSDR

tRDR

VDR

CS2£0.2V

0.4V

GND

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

PACKAGE DIMENSIONS

32 DUAL INLINE PACKAGE (600mil)

Units: millimeters(inches)

+0.10

0.25

-0.05

0.010^+0.004

-0.002

#32

#17

13.60±0.20

0.535±0.008

#16

0~15°

3.81±0.20

0.150±0.008

42.31

1.666

MAX

5.08

0.200

MAX

41.91±0.20

1.650±0.008

3.30±0.30

0.130±0.012

0.46±0.10

0.018±0.004

0.38

0.015

1.91

0.075

1.52±0.10

0.060±0.004

2.54

0.100

MIN

(

)

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8°

#32

#17

14.12±0.30

0.556±0.012

11.43±0.20

0.450±0.008

#16

0.80±0.20

+0.10

-0.05

0.20

2.74±0.20

0.031±0.008

20.87

MAX

0.108±0.008

+0.004

0.822

0.008

-0.002

3.00

0.118

MAX

20.47±0.20

0.806±0.008

0.10 MAX

0.004 MAX

+0.100

-0.050

0.41

0.71

0.028

1.27

0.050

+0.004

-0.002

(

)

0.05

0.002

0.016

MIN

Revision 1.0

September 2003

K6X1008C2D Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

+0.10

-0.05

20.00±0.20

0.787±0.008

0.20

0.008^+0.004

-0.002

#32

0.25

0.010

(

)

8.40

0.331

MAX

0.50

0.0197

#16

#17

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

0.25

0.010

18.40±0.10

0.724±0.004

TYP

+0.10

0.15

-0.05

0.006^+0.004

-0.002

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 1.0

September 2003

K6X1008C2D-TF55相关文章

配单直通车

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K6X1008C2D-TF55产品参数

型号:	K6X1008C2D-TF55
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TSOP1
包装说明：	8 X 20 MM, TSOP1-32
针数：	32
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.32.00.41
风险等级：	5.27
最长访问时间：	55 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G32
JESD-609代码：	e0
长度：	18.4 mm
内存密度：	1048576 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	8
湿度敏感等级：	3
功能数量：	1
端子数量：	32
字数：	131072 words
字数代码：	128000
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	128KX8
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP1
封装等效代码：	TSSOP32,.8,20
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最大待机电流：	0.00001 A
最小待机电流：	2 V
子类别：	SRAMs
最大压摆率：	0.025 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	8 mm
Base Number Matches：	1

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