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CS5528-ASZ 最新到货,只做原装,假一赔十,实体公司,13006613559

日期:2014-4-25 类别: 阅读:2180 (来源:互联网)
公司:
深圳市金和信科技有限公司(原金合讯)
联系人:
陈先生
手机:
13006613559
电话:
086-755-82895713
传真:
086-755-83692623
QQ:
1845848010 1359269554 462452783 66796164 和我即时交谈 和我即时交谈 和我即时交谈 和我即时交谈
地址:
福田区华强广场B座27C

深圳市金合讯科技有限公司

地址:深圳市福田区振华路122号海外装饰大厦A座15A-11室
直线:0755-36853283 13006613559
传真:0755-83692623
邮箱:chenjjm521@163.com
QQ:1845848010
联系人:陈先生
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1. GENERAL DESCRIPTION
The CS5521/22/23/24/28 are highly integrated ΔΣ
Analog-to-DIGITAL Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5521/23) and 24-bit (CS5522/24/28) performance.
The ADCs come as either two-channel
(CS5521/22), four-channel (CS5523/24), or eightchannel
(CS5528) devices, and include a low input
current, chopper-stabilized instrumentation amplifier.
To permit selectable input spans of 25 mV,
55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs include
a PGA (programmable gain amplifier). To
accommodate ground-based thermocouple applications,
the devices include a CPD (Charge Pump
Drive) which provides a negative bias VOLTAGE to
the on-chip amplifiers.
These devices also include a fourth order DS modulator
followed by a digital filter which provides
eight selectable output word rates of 1.88 Sps,
3.76 Sps, 7.51 Sps, 15 Sps, 30 Sps, 61.6 Sps,
84.5 Sps, and 101.1 Sps (XIN = 32.768 kHz). The
devices are capable of producing output update
rates up to 617 Sps when a 200 kHz clock is used
(CS5522/24/28) or up to 401 Sps using a 130 kHz
clock (CS5521/23). Further note that the digital filters
are designed to settle to full accuracy within
one conversion cycle and simultaneously reject
both 50 Hz and 60 Hz interference when operated
at word rates below 30 Sps (assuming a XIN clock
frequency of 32.768 kHz).
To ease communication between the ADCs and a
micro-controller, the converters include an easy to
use three-wire serial interface which is SPI™ and
Microwire™ compatible.
1.1 Analog Input
Figure 4 illustrates a block diagram of the analog input
signal path inside the CS5521/22/23/24/28. The
front end consists of a multiplexer (break before
make configuration), a chopper-stabilized instrumentation
amplifier with fixed gain of 20X,
coarse/fine charge buffers, and a programmable gain
section. For the 25 mV, 55 mV, and 100 mV input
ranges, the input signals are amplified by the 20X instrumentation
amplifier. For the 1 V, 2.5 V, and 5 V
input ranges, the instrumentation amplifier is bypassed
and the input signals are connected to the
Programmable Gain block via coarse/fine charge
buffers.
VREF+
Differential
4th order
delta-sigma
modulator
Digital
Programmable Filter
Gain
VREFNBV
X20
MUX
AIN2+
AIN2-
AIN1+
AIN1-
CS5522