NCP1380BDR2G全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

NCP1380

Quasi-Resonant

Current-Mode Controller for

High-Power Universal

Off-Line Supplies

http://onsemi.com

The NCP1380 hosts a high−performance circuitry aimed to

powering quasi−resonant converters. Capitalizing on a proprietary

valley−lockout system, the controller shifts gears and reduces the

switching frequency as the power loading becomes lighter. This

results in a stable operation despite switching events always occurring

QUASI−RESONANT PWM

CONTROLLER FOR HIGH

POWER AC−DC WALL

ADAPTERS

th

in the drain−source valley. This system works down to the 4 valley

and toggles to a variable frequency mode beyond, ensuring an

excellent standby power performance.

MARKING

To improve the safety in overload situations, the controller includes

an Over Power Protection (OPP) circuit which clamps the delivered

power at high−line. Safety−wise, a fixed internal timer relies on the

feedback voltage to detect a fault. Once the timer elapses, the

controller stops and stays latched for option A and C or enters

auto−recovery mode for option B and D.

DIAGRAMS

8

SOIC−8

D SUFFIX

CASE 751

1380X

ALYWX

G

8

1

Particularly well suited for adapter applications, the controller

features a pin to implement either a combined overvoltage /

overtemperature protection (Version A and B) or a combined

brown−out/overvoltage protection (Version C and D).

1380X = Specific Device Code

X

A

L

= Device Option (A, B, C, or D)

= Assembly Location

= Wafer Lot

Y

W

G

= Year

= Work Week

= Pb−Free Package

Features

• Quasi−Resonant Peak Current−Mode Control Operation

• Valley Switching Operation with Valley−Lockout for Noise−Immune

Operation

• Frequency Foldback at Light Load to Improve the Light Load

Efficiency

PIN CONNECTIONS

ZCD 1

8 CT

• Adjustable Over Power Protection

• Auto−Recovery or Latched Internal Output Short−Circuit Protection

2

3

4

FAULT

VCC

FB

CS

7

6

5

• Fixed Internal 80 ms Timer for Short−Circuit Protection

• Combined Overvoltage and Overtemperature Protection (A and B

Versions)

DRV

GND

• Combined Overvoltage Protection and Brown−Out (C and D

Versions)

• +500 mA / −800 mA Peak Current Source/Sink Capability

• Internal Temperature Shutdown

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 25 of this data sheet.

• Direct Optocoupler Connection

• Extended V Range Operation Up to 28 V

CC

• Extremely Low No−Load Standby Power

• SO−8 Package

• These Devices are Pb−Free and are RoHS Compliant

Typical Applications

• High Power ac−dc Converters for TVs, Set−Top Boxes etc.

• Offline Adapters for Notebooks

1

Publication Order Number:

December, 2009 − Rev. 1

NCP1380/D

NCP1380

TYPICAL APPLICATION EXAMPLE

HV−Bulk

Vout

GND

NCP1380 A/B

ZCD / OPP 1

8

2

7

OVP / OTP

6

5

3

4

GND

Figure 1. Typical Application Schematic for A and B Versions

HV−Bulk

Vout

GND

NCP1380 C/D

1

ZCD / OPP

8

7

6

5

2

3

4

BO / OVP

GND

Figure 2. Typical Application Schematic for C and D Versions

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2

NCP1380

PIN FUNCTION DESCRIPTION

Pin N5

1

Pin Name

Function

Pin Description

ZCD

Zero Crossing Detection

Connected to the auxiliary winding, this pin detects the core

reset event.

Also, injecting a negative voltage smaller than 0.3 V on this

pin will perform over power protection.

Adjust the over power protection

2

FB

Feedback pin

Hooking an optocoupler collector to this pin will allow

regulation.

3

4

5

6

7

CS

Current sense

−

This pin monitors the primary peak.

The controller ground

GND

DRV

Driver output

Supplies the controller

The driver’s output to an external MOSFET

This pin is connected to an external auxiliary voltage.

V

CC

Fault

Over voltage and Over temperature

protection (A and B versions)

Pulling this pin down with an NTC or up with a zener diode

allows to latch the controller.

Over−voltage and Brown−out

protection (C and D versions)

This pin observes the HV rail and protects the circuit in

case of low main conditions. It also offers a way to latch the

circuit in case of over voltage event.

8

C

Timing capacitor

A capacitor connected to this pin acts as the timing

capacitor in foldback mode.

T

NCP1380 OPTIONS

Auto−Recovery

Overcurrent

Protection

Latched

Overcurrent

Protection

OTP

OVP

Yes

Brown−Out

NCP1380 / A

NCP1380 / B

NCP1380 / C

NCP1380 / D

Yes

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3

NCP1380

INTERNAL CIRCUIT ARCHITECTURE

VDD

BO r eset

VCCstop

aux

VCC

latch

V

management

CC

VDD

faul t

Rpullup

gr a nd

reset

FB

LOGIC BLOCK

VDD

ICt

clamp

DRV

gate

Ct

gr a nd

reset

+

DRV

−

Ct setpoint

R

Q

Ct

S

Discharge

CsStop

ZCD

A:

GN D

+

demag

l a tc he d

−

10 V

ESD

Vth

S

DRV

Q

Up

3 ms blanking

IpFlag

TIM ER

Q

Laux

Down

P W Mr eset

Reset

R

SS end

40 ms

Ti me Out

gr a nd

reset

/ 4

The 40 ms Time Out is active

only during s oft−sta r t

V

OVP

VCC

noise delay

VDD

I

OTP(REF)

−

5 ms

SS end

Ti me Out

+

I

= 17.5% V

ILIMIT

PWMreset

IpFlag

peak(VCO)

−

Fault

CS

+

LEB 1

Rsense

noise delay

−

OPP

+

V

OTP

V

ILIMIT

−

Soft-ꢀsꢀtarꢀt

SS end

Soft−sta rt e nd ? the n 1

else 0

CsS top

SS end

+

LEB 2

−

LEB 2 is shorter than LEB 1

V

CS(stop)

Figure 3. Internal Circuit Architecture for Versions A and B

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4

NCP1380

VDD

BO reset

VCCstop

aux

VCC

latch

V

management

faul t

CC

VDD

Rpullup

gr a nd

reset

FB

LOGIC BLOCK

VDD

ICt

clamp

DRV

gate

Ct

gr a nd

reset

DRV

+

−

Ct se tpoint

R

Q

S

Ct

discharge

ZCD

C :

l a tc he d

GN D

+

demag

CsS top

−

10 V

ESD

Vth

IpFlag

S

R

DRV

Q

3 ms blanking

Up

TIMER

Laux

Down

Res et

SS end

P W Mreset

40 ms

Time Out

gr a nd

reset

/ 4

The 40 ms Time Out is active

only during s oft−sta r t

noise delay

5 ms

Time Out

+

VCC

HV

SS end

= 17.5% V

−

I

P W Mreset

IpFlag

peak(VCO)

ILIMIT

VOVP

VDD

IBO

−

CS

+

LEB 1

Rsense

OVP/BO

OPP

VBO

noise delay

+

V

ILIMIT

−

Soft-start

−

Soft−sta r t e nd ? the n 1

Rclamp

Vclamp

BO r es et

else 0

CsS top

SS end

+

LEB 2

LEB 2 is shorter than LEB 1

−

V

CS(stop)

Figure 4. Internal Circuit Architecture for Versions C and D

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5

NCP1380

MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

V

Maximum Power Supply voltage, V pin, continuous voltage

−0.3 to 28

$30

V

mA

CC(MAX)

CC

I

Maximum current for V pin

CC

V

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3 to 20

$1000

V

mA

DRV(MAX)

I

V

Maximum voltage on low power pins (except pins DRV and V

)

CC

−0.3 to 10

$10

V

mA

MAX

CC

I

Current range for low power pins (except pins ZCD, DRV and V

)

I

Maximum current for ZCD pin

+3 / −2

mA

°C/W

°C

ZCD(MAX)

R

Thermal Resistance Junction−to−Air

Maximum Junction Temperature

120

q

JA

T

150

J(MAX)

Operating Temperature Range

−40 to +125

°C

Storage Temperature Range

−60 to +150

°C

ESD Capability, HBM model (Note 1)

ESD Capability, CDM model (Note 1)

4

2

kV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.

Charged Device Model 2000 V per JEDEC Standard JESD22−C101D

2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 3 V,

FB

J

CC

ZCD

V

= 0 V, V

= 1.5 V, C = 680 pF) For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

CS

fault

T

J

CC

Symbol

Condition

Min

Typ

Max

Unit

SUPPLY SECTION − STARTUP AND SUPPLY CIRCUITS

Supply Voltage

V

Startup Threshold

V

increasing

16

8.3

7.2

6.2

6

17

9

8.0

7.2

7

18

9.4

9.2

8.2

8

CC(on)

CC(off)

CC

Minimum Operating Voltage

decreasing

V

Hysteresis V

− V

CC(HYS)

CC(latch)

CC(reset)

CC(on)

CC(off)

Clamped V when latched−off

V

CC

decreasing, I = 30 mA

CC

V

Internal logic reset

t

V

noise filter

CC(reset)

−

5

−

ms

mA

VCC(off)

CC(off)

t

noise filter

20

VCC(reset)

I

Startup current

FB pin open

−

10

4.0

−

20

5.0

−

CC(start)

V

= V

− 0.5 V

CC

CC(on)

I

Current that discharges V when the controller

gets latched

V

CC

= 12 V

3.0

30

mA

CC(disch)

CC

I

Current into V that keeps the controller latched

(Note 3)

V

= V

CC(latch)

CC

CC(latch)

Supply Current

Device Disabled/Fault (Note 3) B, C, and D only

Device Enabled/No output load on pin 5

Device Switching (F

Device Switching VCO mode

mA

I

> V

−

1.7

2.65

2.0

3.0

−

CC1

CC2

CC

sw

CC(off)

F

= 10 kHz

I

= 65 kHz)

C

= 1 nF, F = 65 kHz

= 1 nF, V = 1.25 V

FB

CC3A

CC3B

SW

DRV

SW

CURRENT COMPARATOR − CURRENT SENSE

V

Current Sense Voltage Threshold

Leading Edge Blanking Duration for V

Input Bias Current (Note 3)

V

= 4 V, V increasing

0.76

210

−2

0.8

275

−

0.84

330

2

V

ILIM

LEB

FB

CS

t

Minimum on time minus t

DRV high

ns

mA

ILIM

I

bias

3. Guaranteed by design.

4. The peak current setpoint goes down as the load decreases. It is frozen below I

(I

= cst)

peak(VCO) peak

5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear

6. Minimum value for T = 125°C

J

7. NTC with R

= 8.8 kW.

110

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6

NCP1380

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 3 V,

FB

J

CC

ZCD

V

= 0 V, V

= 1.5 V, C = 680 pF) For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

CS

fault

T

J

CC

Symbol

CURRENT COMPARATOR − CURRENT SENSE

Propagation Delay

Condition

Min

Typ

Max

Unit

t

V

> V to DRV turn−off

ILIM

−

125

175

ns

%

ILIM

peak(VCO)

CS

I

Percentage of maximum peak current level at

which VCO takes over (Note 4)

= 0.4 V, V increasing

15.4

17.5

19.6

FB

CS

V

Setpoint decrease for V

= −300 mV (Note 5)

V

= −300 mV, V = 4 V,

35

37.5

40

%

OPP(MAX)

ZCD

CS

FB

increasing

V

Threshold for immediate fault protection activation

Leading Edge Blanking Duration for V

1.125

1.200

120

1.275

V

CS(stop)

t

−

ns

BCS

CS(stop)

DRIVE OUTPUT − GATE DRIVE

Drive Resistance

W

R

SNK

R

SRC

DRV Sink

V

DRV

V

DRV

= 10 V

= 2 V

−

12.5

20

−

DRV Source

Drive current capability

DRV Sink

DRV Source

mA

I

V

DRV

V

DRV

= 10 V

= 2 V

−

800

500

−

SNK

SRC

I

t

Rise Time (10% to 90%)

Fall Time (90% to 10%)

DRV Low Voltage

C

= 1 nF, V

from 0 to

−

40

75

ns

V

r

DRV

12 V

t

C

DRV

12 V

= 1 nF, V

−

25

60

f

V

= V + 0.2 V

CC(off)

= 1 nF, R

8.4

10.5

9.1

13.0

−

DRV(low)

CC

C

= 33 kW

DRV

V

DRV High Voltage (Note 6)

V

= V

15.5

V

DRV(high)

CC

CC(MAX)

C

= 1 nF

DRV

DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT

V

ZCD threshold voltage

ZCD hysteresis

V

decreasing

increasing

35

15

55

35

90

55

mV

V

ZCD(TH)

ZCD

V

ZCD(HYS)

Input clamp voltage

High state

Low state

V

I

= 3.0 mA

= −2.0 mA

8

−0.9

10

−0.7

12

−0.3

CH

pin1

V

CL

t

Propagation Delay

V

decreasing from 4 V to

−

150

250

ns

DEM

ZCD

−0.3 V

C

Internal input capacitance

−

10

−

pF

ms

PAR

t

Blanking delay after on−time

Timeout after last demag transition

2.30

3.15

4.00

BLANK

t

During soft−start

After the end of soft−start

28

5.0

41

5.9

54

6.7

outSS

t

out

R

Pulldown resistor (Note 3)

140

320

500

kW

ZCD(pdown)

TIMING CAPACITOR

V

Maximum voltage on C pin

V

< V

FB(TH)

5.15

18

−

5.40

20

−

5.65

22

V

CT(MAX)

T

FB

I

Source current

= 0 V

mA

mV

CT

CT(MIN)

CT

V

Minimum voltage on C pin, discharge switch

90

T

activated

C

Recommended timing capacitor value

220

pF

T

3. Guaranteed by design.

4. The peak current setpoint goes down as the load decreases. It is frozen below I

(I

= cst)

peak(VCO) peak

5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear

6. Minimum value for T = 125°C

J

7. NTC with R

= 8.8 kW.

110

http://onsemi.com

7

NCP1380

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 3 V,

FB

J

CC

ZCD

V

= 0 V, V

= 1.5 V, C = 680 pF) For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

CS

fault

T

J

CC

Symbol

FEEDBACK SECTION

Condition

Min

Typ

Max

Unit

R

Internal pullup resistor

15

3.8

18

4.0

0.3

22

4.2

kW

FB(pullup)

I

Pin FB to current setpoint division ratio

ratio

V

FB pin threshold under which C is clamped to

0.26

0.34

V

FB(TH)

T

V

CT(MAX)

Valley threshold

FB voltage where 1 valley ends and 2 valley

starts

FB voltage where 2 valley ends and 3 valley

starts

FB voltage where 3 valley ends and 4 valley

starts

FB voltage where 4 valley ends and VCO starts

st

nd

V

H2D

V

H3D

V

H4D

V

FB

V

FB

V

FB

V

FB

V

FB

V

FB

V

FB

V

FB

decreases

1.316

1.128

0.846

0.732

1.316

1.504

1.692

1.880

1.4

1.2

0.9

0.8

1.4

1.6

1.8

2.0

1.484

1.272

0.954

0.828

1.484

1.696

1.908

2.120

nd

rd

decreases

increases

rd

th

V

HVCOD

th

V

FB voltage where VCO ends and 4 valley starts

HVCOI

th

rd

V

H4I

V

H3I

V

H2I

FB voltage where 4 valley ends and 3 valley

starts

rd

nd

FB voltage where 3 valley ends and 2 valley

starts

nd

st

FB voltage where 2 valley ends and 1 valley

starts

FAULT PROTECTION (ALL VERSIONS)

T

SHDN

Thermal Shutdown

Device switching (F

around 65 kHz)

140

−

170

°C

SW

T

Thermal Shutdown Hysteresis

Overload Timer

−

40

85

−

°C

ms

SHDN(HYS)

t

V

= 4 V, V > V

75

2.8

95

4.8

OVLD

FB

CS

ILIM

t

Soft−start duration

= 4 V, V ramping up,

3.8

SSTART

FB

CS

st

measured from 1 DRV

pulse to V

= 90% of

CS(peak)

V

ILIM

R

Clamp series resistor

1.3

1.55

2.5

30

1.8

kW

V

Fault(clamp)

V

Fault detection level for OVP

Delay before latch confirmation

V

Fault

increasing

2.35

22.5

2.65

37.5

OVP

latch(delay)

t

ms

FAULT PROTECTION A & B VERSIONS

I

Reference current for direct connection of an

NTC (Note 7)

V

= V + 0.2 V

OTP

85

91

97

mA

OTP(REF)

Fault

V

OTP

Fault detection level for OTP

decreasing

0.744

1.13

0.8

0.856

1.57

V

Fault

V

Clamped voltage (Fault pin left open)

Fault pin open

1.35

Fault(clamp)

FAULT PROTECTION C & D VERSIONS

V

Brown−Out level

V

decreasing

0.744

9

0.8

10

0.856

11

V

mA

ms

V

BO

Fault

I

Sourced hysteresis current V

> V

= V + 0.2 V

BO

Fault

BO

Fault

t

Delay before entering and exiting Brown−out

22.5

1.0

30

37.5

1.4

BO(delay)

V

Clamped voltage (Fault pin left open)

Fault pin open

1.2

Fault(clamp)

3. Guaranteed by design.

4. The peak current setpoint goes down as the load decreases. It is frozen below I

(I

= cst)

peak(VCO) peak

5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear

6. Minimum value for T = 125°C

J

7. NTC with R

= 8.8 kW.

110

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8

NCP1380

9.00

17.30

17.25

17.20

17.15

17.10

17.05

17.00

8.95

8.90

8.85

8.80

8.75

8.70

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 5. V_CC(on)vs. Junction Temperature

Figure 6. V_CC(off)vs. Junction Temperature

1.90

1.80

1.70

1.60

1.50

1.40

1.30

2.80

2.70

2.60

2.50

2.40

2.30

2.20

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 7. I_CC2vs. Junction Temperature

Figure 8. I_CC3Avs. Junction Temperature

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

2.40

2.30

2.20

2.10

2.00

1.90

1.80

1.70

1.60

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

Figure 9. I_CC3Bvs. Junction Temperature

T , JUNCTION TEMPERATURE (°C)

Figure 10. I_CC(start)vs. Junction Temperature

J

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9

NCP1380

810

805

800

795

790

785

780

330

310

290

270

250

230

210

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 11. V_ILIMvs. Junction Temperature

Figure 12. T_LEBvs. Junction Temperature

1.265

1.245

1.225

1.205

1.185

1.165

1.145

1.125

39.0

38.5

38.0

37.5

37.0

36.5

36.0

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

Figure 13. V_CS(stop)vs. Junction Temperature

Figure 14. V_OPP(MAX)vs. Junction Temperature

9.4

9.3

9.2

9.1

9.0

8.9

8.8

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 15. V_DRV(low)vs. Junction Temperature

Figure 16. V_DRV(high)vs. Junction Temperature

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10

NCP1380

55

50

45

40

35

30

25

20

15

85

75

65

55

45

35

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 17. V_ZCD(th)vs. Junction Temperature

Figure 18. V_ZCD(hys)vs. Junction Temperature

3.50

3.40

3.30

3.20

3.10

3.0

49.0

47.0

45.0

43.0

41.0

39.0

37.0

35.0

2.90

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 19. T_BLANKvs. Junction Temperature

Figure 20. T_outSSvs. Junction Temperature

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

810

805

800

795

790

785

780

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 21. T_outvs. Junction Temperature

Figure 22. V_OTPvs. Junction Temperature

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11

NCP1380

92.0

91.0

90.0

89.0

88.0

87.0

86.0

810

805

800

795

790

785

780

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 23. I_OTPvs. Junction Temperature

Figure 24. V_BOvs. Junction Temperature

10.4

10.2

10.0

9.8

9.6

9.4

9.2

−40 −20

0

20

40

60

80

100 120

T , JUNCTION TEMPERATURE (°C)

J

Figure 25. I_BOvs. Junction Temperature

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12

NCP1380

APPLICATION INFORMATION

The NCP1380 implements a standard current−mode

architecture operating in quasi−resonant mode. Due to a

proprietary circuitry, the controller prevents

valley−jumping instability and steadily locks out in selected

valley as the power demand goes down. Once the fourth

valley is reached, the controller continues to reduce the

frequency further down, offering excellent efficiency over

a wide operating range. Thanks to a fault timer combined to

an OPP circuitry, the controller is able to efficiently limit the

output power at high−line.

• Quasi−Resonance Current−mode operation:

implementing quasi−resonance operation in peak

current−mode control, the NCP1380 optimizes the

efficiency by switching in the valley of the MOSFET

drain−source voltage. Thanks to a proprietary circuitry,

the controller locks−out in a selected valley and

• Fault input (A and B versions): By combining a dual

threshold on the Fault pin, the controller allows the

direct connection of an NTC to ground plus a zener

diode to a monitored voltage. In case the pin is brought

below the OTP threshold by the NTC or above the OVP

threshold by the zener diode, the circuit permanently

latches−off and V is clamped to 7.2 V.

CC

• Fault input (C and D versions): The C and D versions

of NCP1380 include a brown−out circuit which safely

stops the controller in case the input voltage is too low.

Restart occurs via a complete startup sequence (latch

reset and soft−start). During normal operation, the

voltage on this pin is clamped to V

to give enough

clamp

room for OVP detection. If the voltage on this pin

increases above 2.5 V, the part latches−off.

• Short−circuit protection: Short−circuit and especially

over−load protections are difficult to implement when a

strong leakage inductance between auxiliary and power

windings affects the transformer (where the auxiliary

winding level does not properly collapse in presence of

an output short). Here, when the internal 0.8 V

remains locked until the output loading significantly

changes. When the load becomes lighter, the controller

th

jumps into the next valley. It can go down to the 4

valley if necessary. Beyond this point, the controller

reduces its switching frequency by freezing the peak

current setpoint. During quasi−resonance operation, in

case of very damped valleys, a 5.5 ms timer emulates

the missing valleys.

maximum peak current limit is activated, the timer

starts counting up. If the fault disappears, the timer

counts down. If the timer reaches completion while the

error flag is still present, the controller stops the pulses.

This protection is latched on A and C version (the user

must unplug and re−plug the power supply to restart the

controller) and auto−recovery on B and D versions (if

the fault disappears, the SMPS automatically resumes

operation). In addition, all versions feature a winding

short−circuit protection, that senses the CS signal and

• Frequency reduction in light−load conditions: when

th

the 4 valley is left, the controller reduces the

switching frequency which naturally improves the

standby power by a reduction of all switching losses.

• Overpower protection (OPP): When the voltage on

ZCD pin swings in flyback polarity, a direct image if

the input voltage is applied on ZCD pin. We can thus

reduce the peak current depending of V

during the

stops the controller if V reaches 1.5 x V

(after a

ZCD

CS

ILIM

on−time.

reduced LEB of t ). This additional comparator is

BCS

enabled only during the main LEB duration t

noise immunity reason.

, for

LEB

• Internal soft−start: A soft−start precludes the main

power switch from being stressed upon startup. Its

duration is fixed and equal to 4 ms.

NCP1380 OPERATING MODES

NCP1380 has two operating mode: quasi−resonant

operation and VCO operation for the frequency foldback.

The operating mode is fixed by the FB voltage as

portrayed by Figure 26:

• Quasi−resonant operation occurs for FB voltage higher

than 0.8 V (FB decreasing) or higher than 1.4 V (FB

increasing) which correspond to high output power and

medium output power. The peak current is variable and

is set by the FB voltage divided by 4.

power.

During VCO mode, the peak current decreases down to

17.5% of its maximum value and is then frozen. The

switching frequency is variable and decreases as the

output load decreases.

The switching frequency is set by the end of charge of

the capacitor connected to the C pin. This capacitor is

charged with a constant current source and the

capacitor voltage is compared to an internal threshold

fixed by FB voltage. When this capacitor voltage

reaches the threshold the capacitor is rapidly discharged

down to 0 V and a new period start.

T

• Frequency foldback or VCO mode occurs for FB

voltage lower than 0.8 V (FB decreasing) or lower than

1.4 V (FB increasing). This corresponds to low output

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13

NCP1380

Figure 26. Operating Valley According to FB Voltage

VALLEY DETECTION AND SELECTION

The valley detection is done by monitoring the

detected, an internal counter is incremented. The

operating valley (1^st, 2^nd, 3^rdor 4^th) is determined by

the FB voltage as shown by Figure 26.

voltage of the auxiliary winding of the transformer. A

valley is detected when the voltage on pin 1 crosses

down the 55 mV internal threshold. When a valley is

VDD

Rpullup

FB

V

FB

LOGIC BLOCK

FBth

VDD

S

R

DRV

ICt

Q

Ct

+

−

Ct setpoint

Time Out

CS comparator

Ct

Discharge

ZCD

+

demag

−

10 V

ES D

leakage

blanking

Vth

3 us pulse

DRV

Laux

Figure 27. Valley Detection Circuit

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14

NCP1380

As the output load decreases (FB voltage decreases), the

necessary output power. This allows achieving very low

standby power consumption.

The Figure 28 shows a simulation case where the output

current of a 19 V, 60 W adapter decreases from 2.8 A to

0.1 A. No instability is seen during the valley transitions

(Figures 29, 30, 31 and 32)

valleys are incremented from the first to the fourth. When

the fourth valley is reached, if FB voltage further decreases

below 0.8 V, the controller enters VCO mode.

During VCO operation, the peak current continues to

decrease until it reaches 17.5% of the maximum peak

current: the switching frequency expands to deliver the

Figure 28. Output Load is Decreased from 2.8 A Down to 100 mA at 120 Vdc Input Voltage

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15

NCP1380

Figure 29. Zoom 1: 1^stto 2^ndValley Transition

Figure 30. Zoom 2: 2^ndto 3^rdValley Transition

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16

NCP1380

Figure 31. Zoom 3: 3^rdto 4^thValley Transition

Figure 32. Zoom 4: 4^thValley to VCO Mode Transition

Time Out

In case of extremely damped free oscillations, the ZCD

comparator can be unable to detect the valleys. To avoid

such situation, NCP1380 integrates a Time Out function that

acts as a substitute clock for the decimal counter inside the

logic bloc. The controller thus continues its normal

operation. To avoid having a too big step in frequency, the

time out duration is set to 5.5 ms. Figures 34 and 35 detail the

time out operation.

The NCP1380 also features an extended time out during

the soft−start.

Indeed, at startup, the output voltage reflected on the

auxiliary winding is low. Because of the voltage drop

introduced by the Over Power Compensation diode

(Figure 40), the voltage on the ZCD pin is very low and the

ZCD comparator might be unable to detect the valleys. In

this condition, setting the DRV Latch with the 5.5 ms

time−out can lead to a continuous conduction mode

operation (CCM) at the beginning of the soft−start. This

CCM operation only last a few cycles until the voltage on

ZCD pin becomes high enough to be detected by the ZCD

comparator. To avoid this, the time−out duration is extended

to 40 ms during the soft−start in order to ensure that the

transformer is fully demagnetized before the MOSFET is

turned−on.

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17

NCP1380

VDD

ZCD

+

demag

−

10 V

ES D

LOGIC BLOCK

Vth

leakage blanking

3 us pulse

DRV

SS e nd

5.5 us time out

SS e nd

40 us time out

Figure 33. Time Out Circuit

Figure 34. Time Out Case n51: the 3^rdValley is Missing

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18

NCP1380

Figure 35. Time Out Case n52: the 3^rdand 4^thValley are Missing

VCO MODE OR FREQUENCY FOLDBACK

VCO operation occurs for FB voltage lower than 0.8 V

(FB decreasing), or lower than 1.4 V (FB increasing). This

corresponds to low output power.

Figure 27). When this capacitor voltage reaches the

threshold, the capacitor is rapidly discharged down to 0 V

and a new period start. The internal threshold is inversely

During VCO operation, the peak current is fixed to 17.5%

of his maximum value and the frequency is variable and

expands as the output power decreases.

proportional to FB voltage. The relationship between V

FB

and V

is given by Equation 1.

FBth

V_FBth+ 6.5 * (10ń3)V_FB

(eq. 1)

The frequency is set by the end of charge of the capacitor

When V is lower than 0.3 V, V

is clamped to

FB

CT

connected to the C pin. This capacitor is charged with a

T

V

which is typically 5.5 V. Figure 36 shows the

CT(MAX)

constant current source and its voltage is compared to an

VCO mode at works.

internal threshold (V

) fixed by FB voltage (see

FBth

Figure 36. In VCO Mode, as the Power Output Decreases, the Frequency Expands

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19

NCP1380

SHORT−CIRCUIT OR OVERLOAD MODE

Figure 37 shows the implementation of the fault timer.

S

R

Vd d

Q

DRV

au x

VCC

V

CC

management

latch

VC C sto p

fau l t

grand

reset

CsStop

CS

LEB1

+

PW Mr eset

IpFlag

R sen se

−

FB/4

Down

Up

TIMER

Reset

ZCD/OPP

OPP

+

A&C:

Latched

V

−

ILIMIT

SS en d

Soft −start end ?

Soft−start

S

R

then 1

else 0

Q

Laux

LEB2

+

CsStop

−

grand

reset

V

CS(stop)

Figure 37. Overload Detection Schematic

When the current in the MOSFET is higher than V

/

On A and C versions, when the timers finishes counting

80 ms, the circuit goes in latch mode (Figure 39): the DRV

ILIM

R

, “Max Ip” comparator trips and the digital timer starts

sense

counting: the timer count is incremented each 10 ms. When

the current comes back within safe limits, “Max Ip”

comparator becomes silent and the timer count down: the

timer count is decremented each 10 ms. In normal overload

conditions the timer reaches its completion when it has

counted up 8 times 10 ms.

pulses stop and V is pulled down to V

which is

CC

CC(latch)

7.2 V typically. The circuit un−latches when the current

circulating in V pin drops below I

.

CC(latch)

CC

In parallel to the cycle−by−cycle sensing of the CS pin,

another comparator with a reduced LEB (t ) and a

BCS

threshold of 1.2 V is able to sense winding short−circuit and

immediately shut down the controller. Depending on the

version, this additional protection is either latched or

auto−recovery, according to the overload protection

behavior.

On B and D version, when the timers reaches its

completion, the circuit enter auto−recovery mode: the

circuit stops all operations and V decreases via the circuit

CC

own consumption (I ). When V reaches V , the

CC1

CC

CC(off)

circuit goes in startup mode and restart switching. (see

Figure 38) This ensures a low duty−cycle burst operation in

fault mode.

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20

NCP1380

Figure 38. Auto−Recovery Short−Circuit Protection on B and D Versions

Figure 39. Latched Short−Circuit Protection on A and C Versions

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21

NCP1380

OVER POWER COMPENSATION

The over power compensation is achieved by monitoring

the input voltage. As the auxiliary winding is already

connected to ZCD pin for the valley detection, by selecting

the signal on ZCD pin (pin 1). Indeed, a negative voltage

applied on this pin directly affects the internal voltage

reference setting the maximum peak current (Figure 40).

When the power MOSFET is turned−on, the auxiliary

winding voltage becomes a negative voltage proportional to

the right values for R

and R , we can easily perform

opu

opl

over power compensation.

Rzcd

Ropu

CS

ZCD/OPP

1

IpFlag

OPP

ESD

protection

Ropl

V

ILIMIT

Aux

+

Demag

−

Vth

leakage blanking

Tblank

DRV

Figure 40. Over Power Compensation Circuit

To ensure optimal zero−crossing detection, a diode is

Design example:

V = 18 V

aux

needed to bypass R during the off−time.

opu

If we apply the resistor divider law on the pin 1 during the

V = 0.6 V

d

on−time, we obtain the following relationship:

N

p,aux

= 0.18

R_ZCD) R_opu

N

_p,auxV_in* V_OPP

If we want at least 8 V on ZCD pin, we have:

(eq. 2)

+ *

R_ZCD

R_opl

V_aux* V_d* V_ZCD

R_opl

V_OPP

+

V_ZCD

Where:

is the auxiliary to primary turn ration: N

(eq. 5)

18 * 0.6 * 8

N

/ N

= N

p,aux

aux

[ 1.2

8

p

V is the DC input voltage

in

We can choose: R

= 1 kW and R = 1 kW.

opl

ZCD

V

OPP

is the negative OPP voltage

For the over power compensation, we need to decrease the

peak current by 37.5% at high line (370 Vdc). The

corresponding OPP voltage is:

By selecting a value for R , we can easily deduce R

using Equation 2. While selecting the value for R , we

opl

opu

opl

must be careful not choosing a too low value for this resistor

in order to have enough voltage for zero−crossing detection

during the off−time. We recommend having at least 8 V on

ZCD pin, the maximum voltage being 10 V.

During the off−time, ZCD pin voltage can be expressed as

follows:

V_OPP+ 0.375 V_ILIM+ −300 mV

(eq. 6)

Using Equation 2, we have:

R_ZCD) R_opu

N

_p,auxV_lin* V_OPP

+ *

R_opt

V_OPP

(eq. 7)

(

)

−0.18 370 * −0.3

R_opl

+

+ 221

ǒ _dǓ

V_aux* V

(eq. 3)

V_ZCD

+

(

)

−0.3

R_ZCD) R_opl

Thus,

We can thus deduce the relationship between R and

opl

R_opu+ 221_Ropl* R_ZCD+ 221 1k * 1k + 220 kW

R

ZCD

:

(eq. 8)

R_ZCD

R_opl

V_aux* V_d* V_ZCD

+

(eq. 4)

V_ZCD

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22

NCP1380

OVERVOLTAGE / OVERTEMPERATURE DETECTION (A AND B VERSIONS)

Overvoltage and overtemperature detection is achieved

by reading the voltage on pin 7 (See Figure 41).

VCC

V

OVP

VDD

nois e de lay

−

Dz

+

I

OTP(REF)

OVPcomp

Fa ult

7

S

R

Latch

Q

nois e de lay

−

Rclamp

Vclam p

+

NTC

OT Pcomp

V

OTP

grand

reset

SS end

Figure 41. OVP/OTP Circuitry

The I

current (91 mA typ.) biases the Negative

In case of overvoltage, the zener diode starts to conduct

and inject current inside the internal clamp resistor R

thus causing the pin 7 voltage to increase. When this voltage

reaches the OVP threshold (2.5 V typ), the controller is

OTP(REF)

Temperature Coefficient sensor (NTC), naturally imposing

a dc voltage on the OTP pin. An internal clamp limit the

pin 7 voltage to 1.2 V when the NTC resistance is high (For

clamp

latched−off: all the DRV pulses stops and V

is

example, at 25°C, R

> 100 kW). When the temperature

CC

NTC

pulled−down to V

(7.2 V typ). The circuit

increases, the NTC’s resistance reduces bringing the pin 7

voltage down until it reaches a typical value of 0.8 V: the

comparator trips and latches−off the controller (see

Figure 42).

CC(latch)

un−latches when the current circulating in V pin drops

CC

below I , thus the user must unplug and replug the

CC(latch)

power supply.

Figure 42. Overvoltage and Overtemperature Chronograms

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23

NCP1380

OVERVOLTAGE PROTECTION / BROWN−OUT (C AND D VERSIONS)

The C and D versions of NCP1380 combine brown−out

and overvoltage detection on pin 7.

noise delay

VCC

HV−Bulk

+

S

R

DRV

Q

−

Dz

S

R

Latch

Q

VOVP

VDD

Rbou

OVP/BO

7

IBO

gr a nd

reset

Rbol

noise delay

−

+

Rclamp

CS comp

BO reset

Vclamp

VBO

Figure 43. Brown−out and Overvoltage Protection

In order to protect the power supply against low input

voltage condition, the pin 7 permanently monitors a fraction

of the bulk voltage through a voltage divider. When this

when V reaches V

(Figure 44): this ensures a clean

CC

CC(on)

startup sequence with soft−start. The hysteresis for the

brown−out function is implemented with a high side current

source sinking 10 mA when the brown−out comparator is

image of bulk voltage is below the V

threshold, the

BO

controller stops switching. When the bulk voltage comes

back within safe limits, the circuit will restart pulsing only

high (V

> V

)

bulk

bulk(on)

Figure 44. Brown−out Operating Chronograms

In order to avoid having a too high voltage on pin 7 if the

bulk voltage is high, an internal clamp limits the voltage.

In case of overvoltage, the zener diode will start to

conduct and inject current inside the internal clamp resistor

R

thus causing pin 7 voltage to increase. When this

clamp

voltage reaches V , the controller latches−off and stays

latched until the user cycles down the power supply

(Figure 45).

OVP

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24

NCP1380

Figure 45. Operating Chronograms in Case of Overvoltage

The following equations show how to calculate the

brownout resistors.

First of all, select the bulk voltage value at which the

ǒ_V

_ǓǓ

V_BO

₎* V

(

ǒ

bulk on

bulk off

(eq. 9)

R_bol

+

ǒ_V

I_BO

_BOǓ

₎* V

(

bulk on

controller must start switching (V

) and the bulk

bulk(on)

voltage for shutdown (V

). Then use the following

bulk(off)

ǒ

_BOǓ

R_bolV_{bulk on}₎* V

(

(eq. 10)

equation to calculate R and R

.

bou

bol

R_bou

+

V_BO

ORDERING INFORMATION

Device

†

Package

Shipping

NCP1380ADR2G

SOIC−8

2500 / Tape & Reel

(Pb−Free)

NCP1380BDR2G

NCP1380CDR2G

NCP1380DDR2G

SOIC−8

(Pb−Free)

SOIC−8

(Pb−Free)

SOIC−8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

http://onsemi.com

25

NCP1380

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

B

0.25 (0.010)

Y

1

K

−Y−

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

1.27 BSC

0.050 BSC

−Z−

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

0.10 (0.004)

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

SOLDERING FOOTPRINT*

1.52

0.060

7.0

4.0

0.275

0.155

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

The products described herein (NCP1380), may be covered by one or more of the following U.S. patents; 6,362,067; 5,073,850. There may be other patents

pending.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP1380/D

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26

型号:	NCP1380BDR2G
Brand Name：	ON Semiconductor
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ON SEMICONDUCTOR
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
制造商包装代码：	751-07
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	16 weeks
风险等级：	0.66
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	18 V
最小输入电压：	9.4 V
标称输入电压：	12 V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	SINGLE
最大切换频率：	65 kHz
温度等级：	AUTOMOTIVE
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm

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