NCP1395BDR2G全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

NCP1395A/B

High Performance Resonant

Mode Controller

The NCP1395A/B offers everything needed to build a reliable and

rugged resonant mode power supply. Its unique architecture includes

a 1.0 MHz Voltage Controller Oscillator whose control mode brings

flexibility when an ORing function is a necessity, e.g. in multiple

feedback paths implementations. Protections featuring various

reaction times, e.g. immediate shutdown or timer−based event,

brown−out, broken optocoupler detection etc., contribute to a safer

converter design, without engendering additional circuitry

complexity. An adjustable deadtime also helps lowering the

shoot−through current contribution as the switching frequency

increases.

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MARKING

DIAGRAMS

16

1

16

NCP1395xP

AWLYYWWG

1

PDIP−16

P SUFFIX

CASE 648

Finally, an onboard operational transconductance amplifier allows

for various configurations, including constant output current working

mode or traditional voltage regulation.

Features

16

• High Frequency Operation from 50 kHz up to 1.0 MHz

• Selectable Minimum Switching Frequency with "3% Accuracy

• Adjustable Deadtime from 150 ns to 1.0 ms

• Startup Sequence via an Adjustable Soft−Start

• Brown−Out Protection for a Simpler PFC Association

• Latched Input for Severe Fault Conditions, e.g. Overtemperature

or OVP

1395xDR2G

AWLYWW

1

SO−16

D SUFFIX

CASE 751B

x

A

WL

YY, Y

WW

G

= A or B

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Timer−Based Input with Auto−Recovery Operation for Delayed

Event Reaction

• Enable Input for Immediate Event Reaction or Simple ON/OFF

Control

PIN CONNECTIONS

• Operational Transconductance Amplifier (OTA) for Multiple

Feedback Loops

Fmin

Fmax

DT

1

NINV

Out

16

15

• V Operation up to 20 V

CC

2

3

4

5

6

• Low Startup Current of 300 mA Max

• Common Collector Optocoupler Connection

• Internal Temperature Shutdown

Slow Fault

Fast Fault

Vcc

14

13

Css

FB

12

11

• B Version Features 10 V V Startup Threshold for Auxiliary

CC

Ctimer

BO

B

Supply Usage

A

10

9

7

8

• Easy No−Load Operation and Low Standby Power Due to

Programmable Skip−Cycle

AGnd

PGnd

• These are Pb−Free Devices*

(Top View)

Typical Applications

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 25 of this data sheet.

• LCD/Plasma TV Converters

• High Power Ac−DC Adapters for Notebooks

• Industrial and Medical Power Sources

• Offline Battery Chargers

*For additional information on our Pb−Free strategy

and soldering details, please download the ON

SemiconductorSoldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

©

Semiconductor Components Industries, LLC, 2006

1

Publication Order Number:

March, 2006 − Rev. 1

NCP1395/D

NCP1395A/B

Figure 1. Typical Application Example

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2

NCP1395A/B

PIN FUNCTION DESCRIPTION

Pin No.

Symbol

Function

Description

1

Fmin

Timing Resistor

Connecting a resistor to this pin, sets the minimum oscillator frequency

reached for VFB is below 1.3 V.

2

3

4

5

Fmax

DT

Frequency Clamp

Deadtime

A resistor sets the maximum frequency excursion.

A simple resistor adjusts the deadtime length.

Select the soft−start duration.

Css

FB

Soft−Start

Feedback

Applying a voltage above 1.3 V on this pin increases the oscillation frequency

up to Fmax.

6

7

Ctimer

BO

Timer Duration

Brown−Out

Sets the timer duration in presence of a fault.

Detects low input voltage conditions. When brought above Vlatch, it fully

latches off the controller.

8

Agnd

Pgnd

A

Analog Ground

Power Ground

−

9

−

10

11

12

13

Low Side Output

Drives the low side power MOSFET.

B

High Side Output

Supplies the Controller

Quick Fault Detection

Drives the upper side power MOSFET.

−

Vcc

Fast Fault

Fast shutdown pin, stops all pulses when brought high. Please look in the

description for more details about the fast−fault sequence.

14

Slow Fault

Slow Fault Detection

When asserted, the timer starts to countdown and shuts down the controller at

the end of its time duration.

15

16

OUT

OPAMP Output

Internal transconductance amplifier.

Non−inverting pin of the OPAMP.

NINV

OPAMP Noninverting

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3

NCP1395A/B

Vdd

Temperature

Shutdown

Vref_FB

S

Imin

NINV

Vfb = < Vfb_off

D

Q

+

Vref

+

−

Vref

Clk

+

Fmin

−

gm

R

+

IDT

C

FF

50% DC

DT Adj.

I = Imax for Vfb = 5 V

I = 0 for Vfb < Vfb_off

OUT

BO

Reset

Slow

Fault

Vdd

+

−

PON

Reset

Imax

Vfb = 5

+

SS

Vref Fault

Fault

Vdd

Timeout

Fault

Vref

Fast

Fault

Itimer

+

−

SS Reset on

A Version Only

Fmax

Timer

If FAULT Itimer else 0

+

Vref Fault

+

−

Timeout

Fault

+

Vref

PON

Reset

Fault

20 V

Vdd

V

CC

UVLO

Fault

ISS

SS

FB

B

A

+

−

> 0 only if

V(FB) > Vfb_off

G = 1

Vdd

RFB

−

+

PGND

+

Vfb_fault

Vfb_off

Vref

Deadtime

Adjustment

IDT

DT

Vdd

IBO

BO

+

−

+

−

PON Reset

20 ms Noise

Filter

+

VBO

Vlatch

AGND

Figure 2. Internal Circuit Architecture

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4

NCP1395A/B

MAXIMUM RATINGS

Rating

Symbol

Value

20

Unit

V

Power Supply Voltage, Pin 12

V

CC

Transient Current Injected into V when Internal Zener is Activated –

−

10

mA

CC

Pulse Width < 10 ms

Power Supply Voltage, All Pins (Except Pins 10 and 11)

Thermal Resistance, Junction−to−Air, PDIP Version

Thermal Resistance, Junction−to−Air, SOIC Version

Storage Temperature Range

−

−0.3 to 10

TBD

V

°C/W

°C

R

q

JA

TBD

q

−

−60 to +150

2

ESD Capability, HBM Model (All Pins Except V and HV)

kV

CC

ESD Capability, Machine Model

200

V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per Mil−Std−883, Method 3015

Machine Model Method 200 V.

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

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5

NCP1395A/B

ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = 0°C to +125°C, Max T = 150°C,

j

J

V

CC

= 11 V, unless otherwise noted.)

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY SECTION

Turn−On Threshold Level, V Going Up – A Version

12

VCC

12.3

9.3

8.3

−

13.3

10.3

9.3

3.0

1.0

−

14.3

11.3

10.3

−

V

CC

ON

Turn−On Threshold Level, V Going Up – B Version

CC

ON

Minimum Operating Voltage after Turn−On

VCC

V

(min)

Minimum Hysteresis between VCC and VCC

− A Version

− B Version

VhysteA

VhysteB

Istartup

V

ON

(min)

Minimum Hysteresis between VCC and VCC

−

V

ON

(min)

Startup Current, V < VCC

−

300

−

mA

V

CC

ON

V

CC

Level at which the Internal Logic gets Reset

VCC

−

5.9

1.6

2.3

1.3

reset

Internal IC Consumption, No Output Load on Pins 11/12, Fsw = 300 kHz

Internal IC consumption, 100 pF output load on pin 11 / 12, Fsw = 300 kHz

ICC1

−

mA

ICC2

ICC3

−

Consumption in fault mode (All drivers disabled, Vcc > VCC

)

−

(min)

VOLTAGE CONTROL OSCILLATOR (VCO)

Minimum Switching Frequency, Rt = 120 kW on Pin 1, Vpin 5 = 0 V,

DT = 300 ns

1

2

Fsw min

Fsw max

48.5

0.9

50

51.5

1.11

kHz

Maximum Switching Frequency, Rfmax = 22 kW on Pin 2, Vpin 5 >

1.0

MHz

6.0 V, DT = 300 ns − T = 25°C (Note 3)

j

Feedback Pin Swing above which Df = 0

5

−

FBSW

PSRR

DC

−

6.0

0.2

50

−

V

%/V

%

VCO V Rejection, DV = 1.0 V, in Percentage of Fsw

CC

Operating Duty Cycle

11−10

1, 3

−

48

1.86

−

52

2.14

−

Reference Voltage for all Current Generations (Fosc, DT)

Delay before any Driver Restart in Fault Mode

VREF

Tdel

2.0

20

V

ms

FEEDBACK SECTION

Internal Pulldown Resistor

5

Rfb

VREF_FB

Vfb_off

Vfb_fault

IBias

−

20

2.5

1.3

0.6

−

2.675

−

kW

V

OTA Internal Offset Voltage

16

5

2.325

Voltage on Pin 5 below which the FB Level has no VCO Action

Voltage on Pin 5 below which the Controller Considers a Fault

Input Bias Current

−

V

5

−

V

16

15

100

−

nA

mS

MHz

DC Transconductance Gain

OTAG

250

1.0

Gain Product Bandwidth, Rload = 5.0 kW

GBW

−

DRIVE OUTPUT

Output Voltage Rise Time @ CL = 100 pF, 10−90% of Output Signal

11−10

3

T

−

20

−

ns

W

r

Output Voltage Fall−Time @ CL = 100 pF, 10−90% of Output Signal

T

f

Source Resistance

Sink Resistance

R

OH

20

30

270

−

60

120

130

390

−

R

OL

60

W

Deadtime with R = 127 kW from Pin 3 to GND

T_dead

300

1.0

150

ns

ms

ns

DT

Maximum Deadtime with R = 540 kW from Pin 3 to GND

3

T_dead−max

T_dead−min

DT

Minimum Deadtime, R = 30 kW from Pin 3 to GND

3

−

DT

3. Room temperature only, please look at characterization data for evolution versus junction temperature.

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6

NCP1395A/B

ELECTRICAL CHARACTERISTICS (continued) (For typical values T = 25°C, for min/max values T = 0°C to +125°C,

j

Max T = 150°C, V = 11 V, unless otherwise noted.)

J

CC

Characteristic

Symbol

Min

Typ

Max

Unit

TIMERS

Timer Charge Current

6

4

Itimer

T−timer

T−timerR

VtimerON

VtimerOFF

VSS

−

150

25

−

mA

ms

s

Timer Duration with a 1.0 mF Capacitor and a 1.0 MW Resistor

Timer Recurrence in Permanent Fault, Same Values as Above

Voltage at which Pin 6 Stops Output Pulses

−

1.4

4.1

1.0

2.0

95

−

3.7

0.9

−

4.5

1.1

−

V

Voltage at which Pin 6 Restarts Output Pulses

V

Soft−Start Ending Voltage, V = 1.0 V

V

FB

Soft−Start Charge Current

ISS

75

115

mA

Note 5

Soft−Start Duration with a 220 nF Capacitor (Note 4)

4

T−SS

−

5.0

−

ms

PROTECTION

Reference Voltage for Fast Input

13

14

13

14

13

7

VrefFaultF

VrefFaultS

HysteFaultF

HysteFaultS

TpFault

IBObias

VBO

1.0

0.98

−

1.05

1.03

50

1.1

1.08

−

V

Reference Voltage for Slow Input

Hysteresis for Fast Input

mV

ns

mA

V

Hysteresis for Slow Input

−

40

−

Propagation Delay for Fast Fault Input Drive Shutdown

Brown−Out Input Bias Current

Brown−Out Level

−

70

120

−

0.02

1.03

28

7

0.98

23

70

3.7

140

−

1.08

33

96

4.5

−

Hysteresis Current, Vpin 7 > VBO – A Version

Hysteresis Current, Vpin 7 > VBO – B Version

Latching Voltage

7

IBO_A

mA

V

7

IBO_B

83

7

Vlatch

4.1

−

Temperature Shutdown

−

TSD

°C

Hysteresis

−

TSDhyste

40

−

4. The A version does not activate soft−start when the fast−fault is released, this is for skip cycle implementation. The B version does activate

the soft−start upon release of the fast−fault input.

5. Minimum current occurs at T = 0°C.

J

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7

NCP1395A/B

TYPICAL CHARACTERISTICS − A VERSION

13.5

13.4

13.3

13.2

13.1

13.0

10

9.8

9.6

9.4

9.2

9.0

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 3. VCCon A

Figure 4. VCCmin

50

49.5

49

1.1

1.0

0.9

0.8

0.7

48.5

48

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 5. Fsw min

Figure 6. Fsw max

23

22

21

20

19

18

2.70

2.65

2.60

2.55

2.50

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 8. Pulldown Resistor (RFB)

Figure 7. Reference (Vref_FB)

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8

NCP1395A/B

TYPICAL CHARACTERISTICS − A VERSION

110

100

90

80

70

60

50

40

90

80

70

60

50

40

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 9. Source Resistance (ROH)

Figure 10. Sink Resistance (ROL)

250

230

210

190

170

150

130

350

340

330

320

310

300

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 11. T_dead_min A

Figure 12. T_dead_A

1300

1200

1100

1000

900

1.10

1.08

1.06

1.04

1.02

1.00

800

700

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 14. T_dead_max A

Figure 13. Fast Fault (VrefFault FF)

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9

NCP1395A/B

TYPICAL CHARACTERISTICS − A VERSION

30

1.04

1.035

1.03

29

28

27

1.025

26

25

1.02

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 15. Brown−Out Reference (VBO)

Figure 16. Brown−Out Hysteresis Current (IBO)

4.2

4.15

4.1

4.05

4.0

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 17. Latch Level (Vlatch)

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10

NCP1395A/B

TYPICAL CHARACTERISTICS − B VERSION

11

10.8

10.6

10.4

10.2

10

9.8

9.6

9.4

9.2

9.0

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 18. VCCon B

Figure 19. VCCmin

50

49.5

49

1.1

1.0

0.9

0.8

0.7

48.5

48

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 20. Fsw min

Figure 21. Fsw max

23

22

21

20

19

18

2.70

2.65

2.60

2.55

2.50

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 23. Pulldown Resistor (RFB)

Figure 22. Reference (Vref_FB)

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11

NCP1395A/B

TYPICAL CHARACTERISTICS − B VERSION

110

100

90

80

70

60

50

40

90

80

70

60

50

40

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 24. Source Resistance (ROH)

Figure 25. Sink Resistance (ROL)

250

230

210

190

170

150

130

350

340

330

320

310

300

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 26. T_dead_min B

Figure 27. T_dead_B

1300

1200

1100

1000

900

1.10

1.08

1.06

1.04

1.02

1.00

800

700

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 29. T_dead_max B

Figure 28. Fast Fault (VrefFault FF)

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NCP1395A/B

TYPICAL CHARACTERISTICS − B VERSION

1.04

1.035

1.03

90

85

80

75

70

1.025

1.02

−40 −20

0

20

40

60

80 100 120 140

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 30. Brown−Out Reference (VBO)

Figure 31. Brown−Out Hysteresis Current (IBO)

4.2

4.15

4.1

4.05

4.0

−40 −20

0

20

40

60

80 100 120 140

TEMPERATURE (°C)

Figure 32. Latch Level (Vlatch)

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13

NCP1395A/B

APPLICATION INFORMATION

The NCP1395A/B includes all necessary features to help

28 mA hysteresis current for the lowest consumption

and the B version slightly increases this current to

83 mA in order to improve the noise immunity.

build a rugged and safe switch−mode power supply

featuring an extremely low standby power. The below

bullets detail the benefits brought by implementing the

NCP1395A/B controller:

• Wide Frequency Range: A high−speed Voltage

Control Oscillator allows an output frequency

excursion from 50 kHz up to 1.0 MHz on A and B

outputs.

• Adjustable Fault Timer Duration: When a fault is

detected on the slow fault input or when the FB path is

broken, a timer starts to charge an external capacitor.

If the fault is removed, the timer opens the charging

path and nothing happens. When the timer reaches its

selected duration (via a capacitor on pin 6), all pulses

are stopped. The controller now waits for the

• Adjustable Deadtime: Due to a single resistor wired

to ground, the user has the ability to include some

deadtime, helping to fight cross−conduction between

the upper and the lower transistor.

discharge via an external resistor of pin 6 capacitor to

issue a new clean startup sequence with soft−start.

• Cumulative Fault Events: In the NCP1395A/B, the

timer capacitor is not reset when the fault disappears.

It actually integrates the information and cumulates

the occurrences. A resistor placed in parallel with the

capacitor will offer a simple way to adjust the

• Adjustable Soft−Start: Every time the controller

starts to operate (power on), the switching frequency is

pushed to the programmed maximum value and slowly

moves down toward the minimum frequency, until the

feedback loop closes. The soft−start sequence is

activated in the following cases: a) normal startup

b) back to operation from an off state: during hiccup

faulty mode, brown−out or temperature shutdown

(TSD). In the NCP1395A, the soft−start is not

activated back to operation from the fast fault input,

unless the feedback pin voltage reaches 0.6 V. To the

opposite, in the B version, the soft−start is always

activated back from the fast fault input whatever the

feedback level is.

discharge rate and thus the auto−recovery retry rate.

• Fast and Slow Fault Detection: In some application,

subject to heavy load transients, it is interesting to

give a certain time to the fault circuit, before

activating the protection. On the other hand, some

critical faults cannot accept any delay before a

corrective action is taken. For this reason, the

NCP1395A/B includes a fast fault and a slow fault

input. Upon assertion, the fast fault immediately stops

all pulses and stays in the position as long as the

driving signal is high. When released low (the fault

has gone), the controller has several choices: in the

A version, pulses are back to a level imposed by the

feedback pin without soft−start, but in the B version,

pulses are back through a regular soft−start sequence.

• Adjustable Minimum and Maximum Frequency

Excursion: In resonant applications, it is important to

stay away from the resonating peak to keep operating

the converter in the right region. Due to a single

external resistor, the designer can program its lowest

frequency point, obtained in lack of feedback voltage

(during the startup sequence or in short−circuit

conditions). Internally trimmed capacitors offer a

"3% precision on the selection of the minimum

switching frequency. The adjustable upper stop being

less precise to "15%.

• Skip Cycle Possibility: The absence of soft−start on

the NCP1395A fast fault input offers an easy way to

implement skip cycle when power saving features are

necessary. A simple resistive connection from the

feedback pin to the fast fault input, and skip can be

implemented.

• Low Startup Current: When directly powered from

the high−voltage DC rail, the device only requires

300 mA to startup. In case of an auxiliary supply, the

B version offers a lower startup threshold to cope with

a 12 V dc rail.

• Onboard Transconductance Op Amp: A

transconductance amplifier is used to implement

various options, like monitoring the output current and

maintaining it constant.

• Broken Feedback Loop Detection: Upon startup or

any time during operation, if the FB signal is missing,

the timer starts to charge a capacitor. If the loop is

really broken, the FB level does not grow up before

the timer ends counting. The controller then stops all

pulses and waits that the timer pin voltage collapses to

1.0 V typically before a new attempt to restart, via the

soft−start. If the optocoupler is permanently broken, a

hiccup takes place.

• Brown−Out Detection: To avoid operation from a

low input voltage, it is interesting to prevent the

controller from switching if the high−voltage rail is

not within the right boundaries. Also, when teamed

with a PFC front−end circuitry, the brown−out

detection can ensure a clean startup sequence with

soft−start, ensuring that the PFC is stabilized before

energizing the resonant tank. The A version features a

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14

NCP1395A/B

more recommended for industrial/medical

applications where a 12 V auxiliary supply

directly powers the chip.

• Finally, Two Circuit Versions, A and B: The A and

B versions differ because of the following changes:

1. The startup thresholds are different, the A starts

2. The A version does not activate the soft−start

upon release of the fast fault input. This is to let

the designer implement skip cycle. To the

opposite, the B version goes back to operation

upon the fast fault pin release via a soft−start

sequence.

to pulse for V = 12.8 V whereas the B pulses

CC

for V = 10 V. The turn off levels are the

CC

same, however. The A is recommended for

consumer products where the designer can use

an external startup resistor, whereas the B is

Voltage−Controlled Oscillator

The VCO section features a high−speed circuitry

allowing an internal operation from 100 kHz up to

2.0 MHz. However, as a division by two internally creates

the two Q and Qbar outputs, the final effective signal on

output A and B switches between 50 kHz and 1.0 MHz.

The VCO is configured in such a way that if the feedback

pin goes up, the switching frequency also goes up.

Figure 33 shows the architecture of this oscillator.

FBinternal

Vdd

max

Fsw

+

−

max

Imin

0 to I_Fmax

S

Vref

D

Q

Fmin

+

−

Clk

Rt−m sets

Fmin for V(FB) < Vfb_off

Cint

R

+

Vdd

IDT

A

B

Vref

Imin

DT

Rdt sets

the deadtime

Vdd

Fmax

Vcc

Rt−max sets

the maximum Fsw

FB

−

+

Vfb < Vb_fault

start fault timer

Rfb

20 k

+

Vb_fault

Figure 33. Simplified VCO Architecture

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15

NCP1395A/B

The designer needs to program the maximum switching

Figures 35 and 36 portray the frequency evolution

depending on the feedback pin voltage level in a different

frequency clamp combination.

frequency and the minimum switching frequency. In LLC

configurations, for circuits working above the resonant

frequency, a high precision is required on the minimum

frequency, hence the "3% specification. This minimum

switching frequency is actually reached when no feedback

closes the loop. It can happen during the startup sequence,

a strong output transient loading or in a short−circuit

condition. By installing a resistor from pin 1 to AGND, the

minimum frequency is set. Using the same philosophy,

wiring a resistor from pin 2 to AGND will set the maximum

frequency excursion. To improve the circuit protection

features, we have purposely created a dead zone, where the

feedback loop has no action. This is typically below 1.3 V.

Figure 34 details the arrangement where the internal

voltage (that drives the VCO) varies between 0 and 3.6 V.

However, to create this swing, the feedback pin (to which

the optocoupler emitter connects), will need to swing

typically between 1.3 V and 6.0 V.

F_A&B

No variations

1 MHz

Fmax

D

Fsw = 950 kHz

Fmin

50 kHz

VFB

Fault

area

6 V

1.3 V

D

VFB = 4.7V

0.6 V

Figure 35. Maximal default excursion, Rt = 120 kW

on pin 1 and Rfmax = 35 kW on pin 2.

V

CC

F_A&B

VFB = 1.3−6 V

FB

To VCO

0 to 3.6 V

+

−

No variations

450 kHz

Fmax

Rfb

D

Fsw = 300 kHz

+

1.3 V

Fmin

150 kHz

VFB

Fault

area

6 V

1.3 V

D

VFB = 4.7 V

0.6 V

Figure 34. The OPAMP arrangement limits the VCO

internal modulation signal between 0 and 5.0 V.

Figure 36. Here a different minimum frequency

was programmed as well as a different maximum

frequency excursion.

This technique allows us to detect a fault on the converter

in case the FB pin cannot rise above 1.3 V (to actually close

the loop) in less than a duration imposed by the

programmable timer. Please refer to the fault section for

detailed operation of this mode.

Please note that the previous small signal VCO slope has

now been reduced to 300 k/5.0 = 62.5 kHz/V. This offers

a mean to magnify the feedback excursion on systems

where the load range does not generate a wide switching

frequency excursion. Due to this option, we will see how

it becomes possible to observe the feedback level and

implement skip cycle at light loads. It is important to note

that the frequency evolution does not have a real linear

relationship with the feedback voltage. This is due to the

deadtime presence which stays constant as the switching

period changes.

As shown in Figure 34, the internal dynamics of the

VCO control voltage will be constrained between 0 V and

3.6 V, whereas the feedback loop will drive pin 5 (FB)

between 1.3 V and 6.0 V. If we take the external excursion

numbers, 1.3 V = 50 kHz, 6.0 V = 1.0 MHz, then the VCO

1 Meg−50 k

slope will then be

+ 202 kHzńV.

4.7

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16

NCP1395A/B

1100

The selection of the three setting resistors (Fmax, Fmin

and deadtime) requires the usage of the selection charts

displayed below:

V

CC

= 11 V

1000

900

800

700

600

500

400

300

200

1100

V

CC

= 11 V

FB = 6.5 V

DT = 300 ns

900

700

500

100

0

Fmin = 200 kHz

0

100

200

300

400

500

600

300

100

Rdt (kW)

Fmin = 50 kHz

Figure 39. Dead−Time Resistor Selection

20

70

120

170

220

270

320

370

RFmax (kW)

ORing Capability

If for a particular reason, there is a need for having a

frequency variation linked to an event appearance (instead

of abruptly stopping pulses), then the FB pin lends itself

very well to the addition of other sweeping loops. Several

diodes can easily be used to perform the job in case of

reaction to a fault event or to regulate on the output current

(CC operation). Figure 40 shows how to do it.

Figure 37. Maximum switching frequency resistor

selection depending on the adopted minimum

switching frequency.

200

180

160

140

120

100

80

V

= 11 V

CC

FB = 1 V

DT = 300 ns

V

CC

In1

In2

FB

VCO

20 k

60

40

20

40

60

80

100

120

Figure 40. Due to the FB configuration, loop ORing

is easy to implement.

RFmin (kW)

Figure 38. Minimum Switching Frequency Resistor

Selection

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17

NCP1395A/B

Deadtime Control

Deadtime control is an absolute necessity when the

half−bridge configuration comes to play. The deadtime

technique consists of inserting a period during which both

high and low side switches are off. Of course, the deadtime

amount differs depending on the switching frequency,

hence the ability to adjust it on this controller. The option

ranges between 150 ns and 1.0 ms. The deadtime is actually

made by controlling the oscillator discharge current.

Figure 41 portrays a simplified VCO circuit based on

Figure 33.

Vdd

Icharge:

Fsw min + Fsw max

S

D

Q

+

Clk

−

Idis

R

Ct

+

3 V−1 V

Vref

DT

RDT

A

B

Figure 41. Deadtime Generation

During the discharge time, the clock comparator is high

and unvalidates the AND gates: both outputs are low. When

the comparator goes back to the high level, during the

timing capacitor Ct recharge time, A and B outputs are

validated. By connecting a resistor RDT to ground, it

creates a current whose image serves to discharge the Ct

capacitor: we control the deadtime. The typical range

evolves between 150 ns (RDT = 30 kW) and 1.0 ms (RDT

= 600 kW). Figure 44 shows the typical waveforms

obtained on the output.

circuit. In this controller, a soft−start capacitor connects to

pin 4 and offers a smooth frequency variation upon startup:

when the circuit starts to pulse, the VCO is pushed to the

maximum switching frequency imposed by pin 2. Then, it

linearly decreases its frequency toward the minimum

frequency selected by a resistor on pin 1. Of course,

practically, the feedback loop is suppose to take over the

VCO lead as soon as the output voltage has reached the

target. If not, then the minimum switching frequency is

reached and a fault is detected on the feedback pin

(typically below 600 mV). Figure 43 depicts a typical

frequency evolution with soft−start.

Soft−Start Sequence

In resonant controllers, a soft−start is needed to avoid

suddenly applying the full current into the resonating

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18

NCP1395A/B

1 ires12 vout

20.0

10.0

0

1

−10.0

Ires

SS Action

−20.0

177

Target is

reached

2

175

173

171

169

Vout

200u

600u

1.00m

1.40m

1.80m

time in seconds

Figure 42. Soft−Start Behavior

Figure 43. A Typical Startup Sequence on an LLC

Converter

Please note that the soft−start will be activated in the

following conditions:

• A startup sequence

no soft−start occurs to offer the best skip cycle behavior.

However, it is very possible to combine skip cycle and true

fast fault input, e.g. via ORing diodes driving pin 13. In that

case, if a signal maintains the fast fault input high long

enough to bring the feedback level down (that is to say

below 0.6 V) since the output voltage starts to fall down,

then the soft−start is activated after the release of the pin.

In the B version tailored to operate from an auxiliary

12 V power supply, the soft−start is always activated upon

the fast fault input release, whatever the feedback

condition is.

• During auto−recovery burst mode

• A brown−out recovery

• A temperature shutdown recovery

The fast fault input undergoes a special treatment. Since

we want to implement skip cycle through the fast fault

input on the NCP1395A, we cannot activate the soft−start

every time the feedback pin stops the operations in low

power mode. Therefore, when the fast fault pin is released,

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19

NCP1395A/B

1

vct

2

clock

5 difference

4.00

3.00

2.00

1.00

0

1

16.0

12.0

8.00

4.00

0

2

5

8.00

4.00

0

−4.00

−8.00

56.2u

65.9u

75.7u

85.4u

95.1u

time in seconds

Figure 44. Typical Oscillator Waveforms

Brown−Out Protection

The Brown−Out circuitry (BO) offers a way to protect the

resonant converter from low DC input voltages. Below a

given level, the controller blocks the output pulses, above

it, it authorizes them. The internal circuitry, depicted by

Figure 42, offers a possibility to observe the high−voltage

(HV) rail. A resistive divider made of Rupper and Rlower,

brings a portion of the HV rail on pin 7. Below the turn−on

level, a current source IBO is off. Therefore, the turn−on

level solely depends on the division ratio brought by the

resistive divider.

1 vin 2 vcmp

450 16.0

351 volts

350 12.0

8.00

Vbulk

Vdd

250 volts

Vin

ON/OFF

IBO

BO

250

Rupper

+

−

BO

150 4.00

Rlower

+

VBO

2

50.0

0

BO

1

20.0u

60.0u

100u

140u

180u

time in seconds

Figure 45. The Internal Brown−Out

Configuration with an Offset Current Source

Figure 46. Simulation Results for 350/250 ON/OFF Levels

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20

NCP1395A/B

To the contrary, when the internal BO signal is high

implemented to a) reduce the standby power on the

NCP1395A b) improve the noise immunity on the

NCP1395B. Knowing these values, it becomes possible to

select the turn−on and turn−off levels via a few lines of

algebra:

(A and B pulse), the IBO source is activated and creates

a hysteresis. The hysteresis level actually depends

on the circuit: NCP1395A features a 28 mA whereas

the NCP1395B uses a 83 mA current. Changes are

IBO is off

Rlower

Rlower ) Rupper

(eq. 1)

V()) + Vbulk1

IBO is on

Rlower Rupper

Rlower ) Rupper

Rlower

V()) + Vbulk2

(eq. 2)

ǒ

Ǔ

) IBO

Rlower ) Rupper

We can now extract Rlower from Equation 1 and plug it

into Equation 2, then solve for Rupper:

IBO = 83 mA

Rupper = 1.2 MW

Rlower = 3.4 kW

Vbulk1−VBO

Rupper + Rlower

VBO

The bridge power dissipation is 132 mW when the

front−end PFC stage delivers 400 V. Figure 46 simulation

result confirms our calculations.

Vbulk1−Vbulk2

Rlower + VBO

IBO (Vbulk1−VBO)

If we decide to turn on our converter for Vbulk1 equals

350 V, and turn it off for Vbulk2 equals 250 V, then we

obtain:

Latch−Off Protection

There are some situations where the converter shall be

fully turned off and stay latched. This can happen in

presence of an overvoltage (the feedback loop is drifting)

or when an overtemperature is detected. Due to the addition

of a comparator on the BO pin, a simple external circuit can

lift up this pin above VLATCH (5.0 V typical) and

IBO = 28 mA

Rupper = 3.6 MW

Rlower = 10 kW

2

The bridge power dissipation is 400 /3.601 MW =

permanently disable pulses. The V needs to be cycled

45 mW when the front−end PFC stage delivers 400 V.

CC

down below 5.0 V typically to reset the controller.

V

CC

Vbulk

20 ms

RC

+

−

To permanent

latch

Q1

Vout

+

Vlatch

Rupper

IBO

Vdd

BO

Rlower

+

−

BO

NTC

+

VBO

Figure 47. Adding a comparator on the BO pin offers a way to latch−off the controller.

In Figure 47, Q1 is blocked and does not bother the BO

measurement as long as the NTC and the optocoupler are

not activated. As soon as the secondary optocoupler senses

an OVP condition, or the NTC reacts to a high ambient

temperature, Q1 base is brought to ground and the BO pin

goes up, permanently latching off the controller.

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21

NCP1395A/B

Protection Circuitry

during fault time (please see above for details). The

B version restarts with a soft−start sequence.

This resonant controller differs from competitors due to

its protection features. The device can react to various

inputs like:

• Slow events input: This input serves as a delayed

shutdown, where an event like a transient overload

does not immediately stopped pulses but start a timer.

If the event duration lasts longer than what the timer

imposes, then all pulses are disabled. The voltage on

the timer capacitor (pin 3) starts to decrease until it

reaches 1.0 V. The decrease rate is actually depending

on the resistor the user will put in parallel with the

capacitor, giving another flexibility during design.

• Fast events input: Like an overcurrent condition, a

need to shutdown (sleep mode) or a way to force a

controlled burst mode (skip cycle at low output

power): as soon as the input level exceeds 1.0 V

typical, pulses are immediately stopped. On the

A version, when the input is released, the controller

performs a clean startup sequence without soft−start

unless the feedback voltage goes down below 0.6 V

Figure 48 depicts the architecture of the fault circuitry.

Vdd

Itimer

Ctimer Ctimer

Rtimer

Reset

1 = fault

0 = ok

UVLO

Output

Current

Image

NINV

Vref

+

ON/OFF

+

−

+

−

+

−

Vref Fault

CC Regulation

Compensation

VtimerON

VtimerOFF

1 = ok

0 = fault

Out

−

+

Vref Fault

Slow Fault

Fast Fault

1 = ok

0 = fault

Reset

DRIVING

LOGIC

SS

A

B

A

B

To FB

Fast

Input

Figure 48. This Circuit Combines a Slow and Fast Input for Improved Protection Features

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22

NCP1395A/B

In this figure, the internal OPAMP is used to perform a

reaches the VtimerON level (4.0 V typical), then all pulses

are stopped. Itimer turns off and the capacitor slowly

discharges to ground via a resistor installed in parallel with

it. As a result, the designer can easily determine the time

during which the power supply stays locked by playing on

Rtimer. Now, when the timer capacitor voltage reaches

1.0 V typical (VtimerOFF), the comparator instructs the

internal logic to issues pulses as on a clean soft−start

sequence (soft−start is activated). Please note that the

discharge resistor cannot be lower than 4.0 V/Itimer,

otherwise the voltage on Ctimer will never reach the

turn−off voltage of 4.0 V.

kind of constant current operation (CC) by taking the lead

when the other voltage loop is gone (CV). Due to the ORing

capability on the FB pin, the OPAMP regulates in constant

current mode. When the output reaches a low level close to

a complete short−circuit, the OPAMP output is maximum.

With a resistive divider on the slow fault, this condition can

be detected to trigger the delayed fault. If no OPAMP shall

be used, its input must be grounded.

Slow Input

On this circuit, the slow input goes to a comparator.

When this input exceeds 1.0 V typical, the current source

Itimer turns on, charging the external capacitor Ctimer. If

the fault duration is long enough, when Ctimer voltage

In both cases, when the fault is validated, both outputs A

and B are internally pulled down to ground.

V

CC

FB

Fast Fault

Figure 50. Skip cycle can be

implemented via two

Figure 49. A resistor can easily program the capacitor discharge time.

resistors on the FB pin to the

fast fault input.

Fast Input

Startup Behavior

The fast input is not affected by a delayed action. As soon

as its voltage exceeds 1.0 V typical, all pulses are off and

maintained off as long as the fault is present. When the pin

is released, pulses come back without soft−start for the

A version, with soft−start for the B version.

Due to the low activation level of 1.0 V, this pin can

observe the feedback pin via a resistive divided and thus

implement skip cycle operation. The resonant converter

can be designed to lose regulation in light load conditions,

forcing the FB level to increase. When it reaches the

programmed level, it triggers the fast fault input and stops

When the V voltage grows up, the internal current

consumption is kept to Istup, allowing to crank up the

converter via a resistor connected to the bulk capacitor.

CC

When V reaches the V ON level, output A goes high

CC

first and then output B. This sequence will always be the

same, whatever triggers the pulse delivery: fault, OFF to

ON etc… Pulsing the output A high first gives an

immediate charge of the bootstrap capacitor when an

integrated high voltage half−bridge driver is implemented

such as ON Semiconductor’s NCP5181. Then, the rest of

pulses follow, delivered at the highest switching value, set

by the resistor on pin 2. The soft−start capacitor ensures a

smooth frequency decrease to either the programmed

minimum value (in case of fault) or to a value

corresponding to the operating point if the feedback loop

closes first. Figure 51 shows typical signals evolution at

power on.

pulses. Then V

slowly drops, the loop reacts by

out

decreasing the feedback level which, in turn, unlocks the

pulses: Vout goes up again and so on: we are in skip cycle

mode.

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23

NCP1395A/B

VCC_ON

VCC_(min)

Vcc from an auxiliary supply

SS

FB

T_SS

Fault!

0.6V

A&B

Timer

A

B

A

B

4V

Slopes are similar

1V

Figure 51. At power on, output A is first activated and the frequency slowly

decreases via the soft−start capacitor.

Figure 51 depicts an auto−recovery situation, where the

timer has triggered the end of output pulses. In that case, the

that is to say, when V falls below 10.3 V typical. At this

CC

time, the V pin still receives its bias current from the

CC

V

CC

level was given by an auxiliary power supply, hence

startup resistor and heads toward VCC

via the Vcc

ON

its stability during the hiccup. A similar situation can arise

if the user selects a more traditional startup method,

capacitor. When the voltage reaches VCC , a standard

sequence takes place, involving a soft−start. Figure 52

portrays this behavior.

ON

with an auxiliary winding. In that case, the VCC

(min)

comparator stops the output pulses whenever it is activated,

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24

NCP1395A/B

VCC_ON

VCC_(min)

Vcc from a startup resistor

Fault!

Fault is

released

SS

FB

T_SS

0.6V

A&B

A

B

A

B

Timer

4V

1V

Figure 52. When the V_CCis too low, all pulses are stopped until V_CCgoes back

to the startup voltage.

As described in the data sheet, two startup levels VCC

voltage. To the opposite, for applications where the

ON

are available, via two circuit versions. The NCP1395A

resonant controller is powered from a standby power

supply, the startup level of the NCP1395B of 10 V typically

allows a direct a connection from a 12 V source. Simple

ON/OFF operation is therefore feasible.

features a large hysteresis to allow a classical startup

method with a resistor connected to the bulk capacitor.

Then, at the end of the startup sequence, an auxiliary

winding is supposed to take over the controller supply

ORDERING INFORMATION

Device

Package

Shipping†

NCP1395APG

PDIP−16

(Pb−Free)

25 Units / Rail

NCP1395ADR2G

NCP1395BPG

SOIC−16

(Pb−Free)

2500 Tape & Reel

25 Units / Rail

PDIP−16

(Pb−Free)

NCP1395BDR2G

SOIC−16

(Pb−Free)

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

http://onsemi.com

25

NCP1395A/B

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

CASE 648−08

ISSUE T

NOTES:

−A−

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

16

1

9

8

B

S

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

F

C

L

MIN MAX

A

B

C

D

F

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

SEATING

PLANE

−T−

0.040

0.70

G

H

J

K

L

0.100 BSC

2.54 BSC

1.27 BSC

K

M

0.050 BSC

0.008 0.015

0.110 0.130

0.295 0.305

H

J

0.21

0.38

3.30

7.74

10

G

2.80

7.50

0

D 16 PL

M

0.25 (0.010)

T A

M

S

0

10

_

0.020 0.040

0.51

1.01

SO−16

D SUFFIX

CASE 751B−05

ISSUE J

−A−

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

9

8

−B−

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

B

0.25 (0.010)

1

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

INCHES

MIN

DIM MIN

MAX

10.00

4.00

1.75

0.49

1.25

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

0.386

0.150

0.054

0.014

0.016

F

R X 45

K

_

C

G

J

1.27 BSC

0.050 BSC

−T−

SEATING

PLANE

0.19

0.10

0

0.25

7

0.008

0.004

0

0.009

7

J

M

K

M

P

R

D

16 PL

_

5.80

0.25

6.20

0.50

0.229

0.010

0.244

0.019

M

S

0.25 (0.010)

T

B

A

http://onsemi.com

26

NCP1395A/B

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

Literature Distribution Center for ON Semiconductor

P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada

Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

For additional information, please contact your

local Sales Representative.

NCP1395/D

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27

型号:	NCP1395BDR2G
是否无铅：	不含铅
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	SOIC
包装说明：	LEAD FREE, SOIC-8
针数：	16
Reach Compliance Code：	unknown
风险等级：	5.65
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	RESONANT CONTROL
最大输入电压：	20 V
最小输入电压：	8.3 V
标称输入电压：	11 V
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3
长度：	9.9 mm
湿度敏感等级：	NOT SPECIFIED
功能数量：	1
端子数量：	16
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL
座面最大高度：	1.75 mm
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	1000 kHz
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm
Base Number Matches：	1

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