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December 1997

NDS9430A

Single P-Channel Enhancement Mode Field Effect Transistor

General Description

Features

-5.3A, -20V. R_DS(ON)= 0.05W @ V_GS= -10V

These P-Channel enhancement mode power field effect

transistors are produced using National's proprietary, high cell

density, DMOS technology. This very high density process is

especially tailored to minimize on-state resistance, provide

superior switching performance, and withstand high energy

pulses in the avalanche and commutation modes. These

devices are particularly suited for low voltage applications such

as notebook computer power management and other battery

powered circuits where fast switching, low in-line power loss,

and resistance to transients are needed.

R_DS(ON)= 0.065W @ V_GS= -6V

R_DS(ON)= 0.09W @ V_GS= -4.5V.

High density cell design for extremely low R_DS(ON).

High power and current handling capability in a widely used

surface mount package.

___________________________________________________________________________________________

4

3

2

1

5

6

7

8

Absolute Maximum Ratings T_A= 25°C unless otherwise noted

Symbol Parameter

NDS9430A

-20

Units

Drain-Source Voltage

Gate-Source Voltage

Drain Current - Continuous

- Pulsed

V

A

V_DSS

V_GSS

I_D

± 20

(Note 1a)

± 5.3

± 20

P_D

Maximum Power Dissipation

(Note 1a)

(Note 1b)

2.5

W

1.2

(Note 1c)

1

T_J,T_STG

Operating and Storage Temperature Range

-55 to 150

°C

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

(Note 1a)

(Note 1)

50

25

°C/W

R

JA

q

Thermal Resistance, Junction-to-Case

R

JC

q

NDS9430A Rev.A

Electrical Characteristics (T_A= 25°C unless otherwise noted)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

OFF CHARACTERISTICS

BV_DSS

I_DSS

Drain-Source Breakdown Voltage

V_GS= 0 V, I_D= -250 µA

V_DS= -16 V, V_GS= 0 V

V_DS= -10 V, V_GS= 0 V

V_GS= 20 V, V_DS= 0 V

V_GS= -20 V, V_DS= 0 V

-20

V

Zero Gate Voltage Drain Current

-1

-5

µA

nA

T_J= 70°C

Gate - Body Leakage, Forward

Gate - Body Leakage, Reverse

100

-100

I_GSSF

I_GSSR

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage

-1

-1.4

-1

-3

-2

V

V_GS(th)

V_DS= V_GS, I_D= -250 µA

V_GS= -10 V, I_D= -5.3 A

-0.7

T_J= 125°C

Static Drain-Source On-Resistance

0.038

0.054

0.046

0.064

0.05

0.1

R_DS(ON)

W

V_GS= -6 V, I_D= -4.7 A

V_GS= -4.5 V, I_D= -4.2 A

V_GS= -10 V, V_DS= -5 V

V_GS= -4.5, V_DS= -5V

0.065

0.09

I_D(on)

On-State Drain Current

-15

A

S

-3.6

g_FS

Forward Transconductance

V_DS= 15 V, I_D= 5.3 A

10

DYNAMIC CHARACTERISTICS

Input Capacitance

950

610

220

pF

C_iss

C_oss

C_rss

V_DS= 15 V, V_GS= 0 V,

f = 1.0 MHz

Output Capacitance

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2)

Turn - On Delay Time

Turn - On Rise Time

Turn - Off Delay Time

Turn - Off Fall Time

Total Gate Charge

10

18

80

45

29

3

30

60

ns

t_D(on)

t_r

t_D(off)

t_f

V_DD= -10 V, I_D= -1 A,

V_GEN= -10 V, R_GEN= 6 W

120

100

50

ns

nC

Q_g

Q_gs

Q_gd

V_DS= -10 V,

I_D= -5.3 A, V_GS= -10 V

Gate-Source Charge

Gate-Drain Charge

9

NDS9430A Rev.A

Electrical Characteristics (T_A= 25°C unless otherwise noted)

Symbol Parameter Conditions

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

Min

Typ

Max Units

Maximum Continuous Drain-Source Diode Forward Current

-2.1

-1.2

100

A

V

I_S

Drain-Source Diode Forward Voltage

Reverse Recovery Time

-0.85

V_SD

t_rr

V_GS= 0 V, I_S= -2.4 A (Note 2)

ns

V_GS= 0V, I_F= -2.4 A, dI_F/dt = 100 A/µs

Notes:

1. R_q_JAis the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R_q_JCis guaranteed by

design while R_q_CAis determined by the user's board design.

T - T

= I²_D(t) ´ R_{DS(ON )}

J

A

J

A

( )

P_Dt =

=

(t)

T

R

+R

t

CA

( )

qJ

A

q

J

C

Typical R_q_JAusing the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

a. 50^oC/W when mounted on a 1 in²pad of 2oz cpper.

b. 105^oC/W when mounted on a 0.04 in²pad of 2oz cpper.

c. 125^oC/W when mounted on a 0.006 in²pad of 2oz cpper.

1a

1b

1c

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDS9430A Rev.A

Typical Electrical Characteristics

-30

3

2.5

2

V_GS=-10V

-6.0

-5.0

-25

-4.5

V_GS= -3.5V

-4.0

-20

-15

-10

-5

-4.0V

-4.5V

-5.0V

-3.5

1.5

1

-6.0V

-3.0

-4

-10V

0

0.5

0

-4

-8

-12

-16

-20

150

0

-1

-2

-3

-5

V

, DRAIN-SOURCE VOLTAGE (V)

I

D

, DRAIN CURRENT (A)

DS

Figure 1. On-Region Characteristics

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage

1.6

1.4

1.2

1

2

1.5

1

V_GS= -10V

I_D= -5.3A

V

= -10V

GS

T

= 125°C

J

25°C

-55°C

0.8

0.6

0.5

-50

-25

0

T

25

50

75

100

125

150

0

-5

-10

, DRAIN CURRENT (A)

-15

I

, JUNCTION TEMPERATURE (°C)

D

J

Figure 4. On-Resistance Variation

with Drain Current and Temperature

Figure 3. On-Resistance Variation

with Temperature

-20

1.2

1.1

1

T

= -55°C

J

25

V_DS= -10V

V_DS= V_GS

125

I_D= -250µA

-16

-12

-8

0.9

0.8

0.7

0.6

-4

0

-1

-2

-V

-3

-4

-5

-50

-25

0

25

, JUNCTION TEMPERATURE (°C)

J

50

75

100

125

, GATE TO SOURCE VOLTAGE (V)

T

GS

Figure 6. Gate Threshold Variation

with Temperature

Figure 5. Transfer Characteristics

NDS9430A Rev.A

Typical Electrical Characteristics (continued)

1.1

20

10

5

I_D= -250µA

1.08

V_GS= 0V

1.06

1.04

1.02

1

0.1

T

= 125°C

J

25°C

-55°C

0.98

0.96

0.94

0.01

0.001

-50

-25

0

25

50

75

100

125

150

0

0.3

-V

0.6

0.9

1.2

1.5

T

, JUNCTION TEMPERATURE (°C)

, BODY DIODE FORWARD VOLTAGE (V)

SD

J

Figure 7. Breakdown Voltage

Variation with Temperature

Figure 8. Body Diode Forward Voltage Variation

with Source Current and

Temperature

3000

2000

10

V_DS= -10V

I _D= -5.3A

-15V

-20V

8

6

4

2

0

C

iss

1000

500

C

oss

300

200

C

rss

f = 1 MHz

V_GS= 0V

100

0.1

0.3

-V

1

3

10

30

0

10

20

, GATE CHARGE (nC)

30

40

, DRAIN TO SOURCE VOLTAGE (V)

Q

g

DS

Figure 10. Gate Charge Characteristics

Figure 9. Capacitance Characteristics

t_on

t_off

-V_DD

t_d(off)

t_d(on)

t_f

t_r

R_L

90%

V_IN

90%

D

V_OUT

V

OUT

V_GS

10%

R_GEN

DUT

G

90%

V

50%

IN

S

10%

INVERTED

PULSE W IDTH

Figure 12. Switching Waveforms

Figure 11. Switching Test Circuit

NDS9430A Rev.A

Typical Electrical and Thermal Characteristics (continued)

2.5

20

V_DS= -15V

1a

T

= -55°C

J

16

12

8

2

1.5

1

25°C

125°C

1b

1c

4.5"x5" FR-4 Board

T_A

25^o

Still Air

4

=

C

0.5

0

0.2

0.4

0.6

0.8

1

0

-5

-10

, DRAIN CURRENT (A)

-15

-20

2

2oz COPPER MOUNTING PAD AREA (in

)

I

D

Figure 14. SO-8 Maximum Steady-State Power

Dissipation versus Copper Mounting Pad

Area.

Figure 13. Transconductance Variation with Drain

Current and Temperature

6

5

30

10

1a

3

1

1b

4

1c

0.3

0.1

V_GS= -10V

SINGLE PULSE

3

4.5"x5" FR-4 Board

R

= See Note 1c

JA

T_A

Still Air

= C

25 ^o

q

0.03

0.01

T_A= 25°C

V_GS

=

-10V

2

0

0.2

0.4

0.6

0.8

1

0.1

0.2

0.5

1

2

5

10

30

50

2

)

2oz COPPER MOUNTING PAD AREA (in

- V

DS

, DRAIN-SOURCE VOLTAGE (V)

Figure 15. Maximum Steady-State Drain

Current versus Copper Mounting Pad

Area.

Figure 16. Maximum Safe Operating Area

1

D = 0.5

0.2

0.5

0.2

0.1

R

(t) = r(t) * R

JA

q

JA

q

R

= See Note 1c

0.1

0.05

JA

q

0.05

P(pk)

0.02

0.01

Single Pulse

0.02

0.01

t

1

t

2

0.005

T

- T

= P * R

(t)

2

J

JA

A

q

Duty Cycle, D = t / t

1

0.002

0.001

0.0001

0.001

0.01

0.1

1

10

100

300

t₁, TIME (sec)

Figure 17. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

NDS9430A Rev.A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

â

SMART START™

STAR*POWER™

Stealth™

VCX™

FAST

ACEx™

Bottomless™

CoolFET™

OPTOLOGIC™

OPTOPLANAR™

PACMAN™

FASTr™

FRFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

GlobalOptoisolator™

GTO™

HiSeC™

ISOPLANAR™

LittleFET™

MicroFET™

MicroPak™

MICROWIRE™

CROSSVOLT™

DenseTrench™

DOME™

POP™

Power247™

PowerTrench^â

QFET™

EcoSPARK™

E²CMOS^TM

TinyLogic™

QS™

EnSigna^TM

TruTranslation™

UHC™

QT Optoelectronics™

Quiet Series™

SILENTSWITCHER^â

FACT™

FACT Quiet Series™

UltraFET^â

STAR*POWER is used under license

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or

In Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. H4

型号:	NDS9430A_NL
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	SOT
包装说明：	SMALL OUTLINE, R-PDSO-G8
针数：	8
Reach Compliance Code：	unknown
ECCN代码：	EAR99
风险等级：	5.3
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	20 V
最大漏极电流 (Abs) (ID)：	5.3 A
最大漏极电流 (ID)：	5.3 A
最大漏源导通电阻：	0.05 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
元件数量：	1
端子数量：	8
工作模式：	ENHANCEMENT MODE
最高工作温度：	150 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
极性/信道类型：	P-CHANNEL
最大功率耗散 (Abs)：	1 W
认证状态：	Not Qualified
子类别：	Other Transistors
表面贴装：	YES
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子位置：	DUAL
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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