OPA637AU各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号OPA637AU的概述

OPA637AU 芯片概述 OPA637AU是一种高性能运算放大器，广泛用于各种高精度模拟信号处理应用。该芯片具有超低噪声特性和宽带宽，使其在音频、医疗仪器和精密测量等领域表现优异。OPA637AU的设计旨在满足高增益、高频率和低失真等要求，因而适合用于多种高端系统。 OPA637AU 采用许多先进的技术特性以优化其性能。这些特性不仅提高了信号的准确性，还确保了在广泛条件下的稳定性。其优良的线性度、快速的瞬态响应和极低的失真，使其在各种应用中均能够提供卓越的性能。这一系列的优点使得OPA637AU成为设计工程师的首选组件之一。 OPA637AU 的详细参数 OPA637AU 的主要技术参数如下： - 参考电源电压范围：±2V 至 ±18V，可以实现广泛的供电配置。 - 增益带宽积：125MHz - 输入失调电压：小于 0.2mV - 输入失调电压漂移：±0.5 μV/°C - 输入阻抗...

产品型号OPA637AU的Datasheet PDF文件预览

OPA627

OPA637

OPA627

Precision High-Speed

Difet ^®OPERATIONAL AMPLIFIERS

APPLICATIONS

● PRECISION INSTRUMENTATION

FEATURES

● VERY LOW NOISE: 4.5nV/√Hz at 10kHz

● FAST DATA ACQUISITION

● FAST SETTLING TIME:

OPA627—550ns to 0.01%

OPA637—450ns to 0.01%

● DAC OUTPUT AMPLIFIER

● OPTOELECTRONICS

● LOW V_OS: 100µV max

● SONAR, ULTRASOUND

● LOW DRIFT: 0.8µV/°C max

● LOW I_B: 5pA max

● HIGH-IMPEDANCE SENSOR AMPS

● HIGH-PERFORMANCE AUDIO CIRCUITRY

● OPA627: Unity-Gain Stable

● OPA637: Stable in Gain ≥ 5

● ACTIVE FILTERS

High frequency complementary transistors allow in-

creased circuit bandwidth, attaining dynamic perform-

ance not possible with previous precision FET op

amps. The OPA627 is unity-gain stable. The OPA637

is stable in gains equal to or greater than five.

DESCRIPTION

The OPA627 and OPA637 Difet operational amplifi-

ers provide a new level of performance in a precision

FET op amp. When compared to the popular OPA111

op amp, the OPA627/637 has lower noise, lower offset

voltage, and much higher speed. It is useful in a broad

range of precision and high speed analog circuitry.

Difet fabrication achieves extremely low input bias

currents without compromising input voltage noise

performance. Low input bias current is maintained

over a wide input common-mode voltage range with

unique cascode circuitry.

The OPA627/637 is fabricated on a high-speed, dielec-

trically-isolated complementary NPN/PNP process. It

operates over a wide range of power supply voltage—

±4.5V to ±18V. Laser-trimmed Difet input circuitry

provides high accuracy and low-noise performance

comparable with the best bipolar-input op amps.

The OPA627/637 is available in plastic DIP, SOIC

and metal TO-99 packages. Industrial and military

temperature range models are available.

+V_S

Trim

Output

+In

–In

Difet ^®, Burr-Brown Corp.

–V_S

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-998H

Printed in U.S.A. March, 1998

SPECIFICATIONS

ELECTRICAL

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

OPA627BM, BP, SM

OPA637BM, BP, SM

OPA627AM, AP, AU

OPA637AM, AP, AU

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

(1)

OFFSET VOLTAGE

Input Offset Voltage

AP, BP, AU Grades

Average Drift

AP, BP, AU Grades

Power Supply Rejection

100

0.4

0.8

120

100

250

0.8

130

280

1.2

2.5

116

250

500

µV

µV/°C

V_S= ±4.5 to ±18V

106

100

INPUT BIAS CURRENT ⁽²⁾

Input Bias Current

Over Specified Temperature

SM Grade

Over Common-Mode Voltage

Input Offset Current

Over Specified Temperature

SM Grade

V_CM= 0V

V_CM= ±10V

V_CM= 0V

0.5

NOISE

Input Voltage Noise

Noise Density: f = 10Hz

f = 100Hz

f = 1kHz

f = 10kHz

Voltage Noise, BW = 0.1Hz to 10Hz

Input Bias Current Noise

Noise Density, f = 100Hz

Current Noise, BW = 0.1Hz to 10Hz

5.2

4.5

0.6

1.6

5.6

4.8

0.8

nV/√Hz

µVp-p

1.6

2.5

fA/√Hz

fAp-p

INPUT IMPEDANCE

Differential

Common-Mode

10¹³|| 8

10¹³|| 7

Ω || pF

INPUT VOLTAGE RANGE

Common-Mode Input Range

Over Specified Temperature

Common-Mode Rejection

±11

±10.5

106

±11.5

±11

116

V_CM= ±10.5V

100

110

OPEN-LOOP GAIN

Open-Loop Voltage Gain

Over Specified Temperature

SM Grade

_O= ±10V, R_L= 1kΩ

112

106

100

120

117

114

106

100

116

110

V_O= ±10V, R_L= 1kΩ

FREQUENCY RESPONSE

Slew Rate: OPA627

OPA637

Settling Time: OPA627 0.01%

0.1%

G = –1, 10V Step

G = –4, 10V Step

G = –1, 10V Step

G = –4, 10V Step

G = 1

100

135

550

450

300

0.00003

V/µs

OPA637 0.01%

0.1%

Gain-Bandwidth Product: OPA627

OPA637

Total Harmonic Distortion + Noise

MHz

G = 10

G = +1, f = 1kHz

POWER SUPPLY

Specified Operating Voltage

Operating Voltage Range

Current

±15

±7

±4.5

±18

±7.5

OUTPUT

Voltage Output

Over Specified Temperature

Current Output

Short-Circuit Current

Output Impedance, Open-Loop

_L= 1kΩ

±11.5

±11

±12.3

±11.5

±45

+70/–55

V_O= ±10V

Ω

±35

±100

1MHz

TEMPERATURE RANGE

Specification: AP, BP, AM, BM, AU

–25

–55

–60

–40

+85

°C

Storage: AM, BM, SM

AP, BP, AU

+125

+150

+125

°C

θ_J-A: AM, BM, SM

AP, BP

200

100

160

°C/W

* Specifications same as “B” grade.

NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at T_J= +25°C. See Typical Performance Curves for warmed-up performance.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

OPA627, 637

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN CONFIGURATIONS

Supply Voltage .................................................................................. ±18V

Input Voltage Range .............................................. +V_S+ 2V to –V_S– 2V

Differential Input Range....................................................... Total V_S+ 4V

Power Dissipation ........................................................................ 1000mW

Operating Temperature

M Package .................................................................. –55°C to +125°C

P, U Package ............................................................. –40°C to +125°C

Storage Temperature

Top View

DIP/SOIC

Offset Trim

–In

No Internal Connection

+V_S

+In

Output

Offset Trim

M Package .................................................................. –65°C to +150°C

P, U Package ............................................................. –40°C to +125°C

Junction Temperature

–V_S

M Package .................................................................................. +175°C

P, U Package ............................................................................. +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

SOlC (soldering, 3s) ................................................................... +260°C

NOTE: (1) Stresses above these ratings may cause permanent damage.

TO-99

Top View

No Internal Connection

PACKAGE/ORDERING INFORMATION

+V_S

Offset Trim

PACKAGE DRAWING

NUMBER⁽¹⁾

TEMPERATURE

RANGE

PRODUCT

PACKAGE

OPA627AP

OPA627BP

OPA627AU

OPA627AM

OPA627BM

OPA627SM

Plastic DIP

SOIC

TO-99 Metal

006

182

001

–25°C to +85°C

–55°C to +125°C

–In

Output

+In

OPA637AP

OPA637BP

OPA637AU

OPA637AM

OPA637BM

OPA637SM

Plastic DIP

SOIC

TO-99 Metal

006

182

001

–25°C to +85°C

–55°C to +125°C

Offset Trim

–V_S

Case connected to –V_S.

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

OPA627, 637

TYPICAL PERFORMANCE CURVES

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH

INPUT VOLTAGE NOISE SPECTRAL DENSITY

100

p-p

Noise Bandwidth:

0.1Hz to indicated

frequency.

100

0.1

RMS

0.01

100

10k

100k

10M

100

10k

100k

10M

Bandwidth (Hz)

Frequency (Hz)

VOLTAGE NOISE vs SOURCE RESISTANCE

OPEN-LOOP GAIN vs FREQUENCY

100

140

120

100

–

OPA637

R_S

Comparison with

OPA27 Bipolar Op

Amp + Resistor

OPA627 + Resistor

OPA627

Spot Noise

at 10kHz

Resistor Noise Only

–20

100

10k

100k

10M

100M

100

10k 100k 1M

10M 100M

Ω

)

Source Resistance (

Frequency (Hz)

OPA627 GAIN/PHASE vs FREQUENCY

OPA637 GAIN/PHASE vs FREQUENCY

–90

–120

–150

–180

–210

–120

–150

–180

–210

Phase

Gain

75° Phase

Margin

Gain

–10

100

Frequency (MHz)

OPA627, 637

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

OPEN-LOOP GAIN vs TEMPERATURE

OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY

125

120

115

110

105

100

200

20k

200k

20M

–75 –50

–25

100 125

Frequency (Hz)

Temperature (°C)

COMMON-MODE REJECTION vs

INPUT COMMON MODE VOLTAGE

COMMON-MODE REJECTION vs FREQUENCY

OPA637

130

120

110

100

140

120

100

OPA627

100

10k

100k

10M

–15

–10

–5

Common-Mode Voltage (V)

Frequency (Hz)

POWER-SUPPLY REJECTION AND COMMON-MODE

REJECTION vs TEMPERATURE

POWER-SUPPLY REJECTION vs FREQUENCY

125

120

115

110

105

140

120

100

PSR

–V_SPSRR 627

and 637

CMR

+V_SPSRR 627

637

–75

–50

–25

100

125

100

10k

100k

10M

Frequency (Hz)

Temperature (°C)

OPA627, 637

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

SUPPLY CURRENT vs TEMPERATURE

OUTPUT CURRENT LIMIT vs TEMPERATURE

100

7.5

+I_Lat V_O= 0V

+I_Lat V_O= +10V

–I_Lat V_O= 0V

6.5

–I_Lat V_O= –10V

–75 –50

–25

100 125

–75 –50

–25

100

125

Temperature (°C)

OPA637 GAIN-BANDWIDTH AND SLEW RATE

vs TEMPERATURE

OPA627 GAIN-BANDWIDTH AND SLEW RATE

vs TEMPERATURE

120

100

160

Slew Rate

140

120

100

Slew Rate

GBW

–75

–50

–25

100

125

–75

–50

–25

100

125

Temperature (°C)

OPA627 TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY

OPA637 TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY

0.1

0.01

0.1

G = +1

G = +10

G = +50

V_I

–

V_O= ±10V

–

V_O= ±10V

V_I

–

V_O= ±10V

600

–

V_O= ±10V

600

600 Ω

600Ω

5kΩ

100pF

Ω

5kΩ

100pF

549Ω

549

Ω

102

Ω

Measurement BW: 80kHz

0.001

0.01

G = +50

Measurement BW: 80kHz

G = +10

0.0001

0.00001

0.001

0.0001

G = +1

G = +10

10k 20k

100

10k 20k

100

Frequency (Hz)

OPA627, 637

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

INPUT BIAS CURRENT

vs POWER SUPPLY VOLTAGE

INPUT BIAS AND OFFSET CURRENT

vs JUNCTION TEMPERATURE

10k

NOTE: Measured fully

warmed-up.

TO-99

Plastic

100

I_B

DIP, SOIC

I_OS

TO-99 with 0807HS Heat Sink

0.1

±4

±6

±8

±10

±12

±14

±16

±18

–50 –25

100

125 150

Supply Voltage (±V_S)

Junction Temperature (°C)

INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE

INPUT OFFSET VOLTAGE WARM-UP vs TIME

1.2

1.1

Beyond Linear

Common-Mode Range

0.9

0.8

–25

–50

Beyond Linear

Common-Mode Range

–15

–10

–5

Common-Mode Voltage (V)

Time From Power Turn-On (Min)

MAX OUTPUT VOLTAGE vs FREQUENCY

SETTLING TIME vs CLOSED-LOOP GAIN

100

Error Band: ±0.01%

OPA627

OPA637

OPA627

0.1

100k

10M

100M

–1

–10

–100

–1000

Frequency (Hz)

Closed-Loop Gain (V/V)

OPA627, 637

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, and V_S= ±15V, unless otherwise noted.

SETTLING TIME vs ERROR BAND

SETTLING TIME vs LOAD CAPACITANCE

1500

1000

500

C_F

+5V

–5V

OPA627 OPA637

R_I

R_F

OPA637

G = –4

–

R_I2kΩ

R_F2kΩ

C_F6pF

500Ω

2kΩ

4pF

Error Band:

±0.01%

2kΩ

OPA627

G = –1

OPA627

G = –1

OPA637

G = –4

0.001

0.01

0.1

Error Band (%)

150

200

300

400

500

Load Capacitance (pF)

APPLICATIONS INFORMATION

R_F< 4R_I

OPA627

The OPA627 is unity-gain stable. The OPA637 may be used

to achieve higher speed and bandwidth in circuits with noise

gain greater than five. Noise gain refers to the closed-loop

gain of a circuit as if the non-inverting op amp input were

being driven. For example, the OPA637 may be used in a

non-inverting amplifier with gain greater than five, or an

inverting amplifier of gain greater than four.

OPA627

–

Buffer

Non-Inverting Amp

G < 5

R_I

R_F< 4R

R_I

When choosing between the OPA627 or OPA637, it is

important to consider the high frequency noise gain of your

circuit configuration. Circuits with a feedback capacitor

(Figure 1) place the op amp in unity noise-gain at high

frequency. These applications must use the OPA627 for

proper stability. An exception is the circuit in Figure 2,

where a small feedback capacitance is used to compensate

for the input capacitance at the op amp’s inverting input. In

this case, the closed-loop noise gain remains constant with

frequency, so if the closed-loop gain is equal to five or

greater, the OPA637 may be used.

OPA627

–

Bandwidth

Limiting

Inverting Amp

G < |–4|

OPA627

–

Filter

Integrator

FIGURE 1. Circuits with Noise Gain Less than Five Require

the OPA627 for Proper Stability.

OPA627, 637

OFFSET VOLTAGE ADJUSTMENT

amp contributes little additional noise. Below 1kΩ, op amp

noise dominates over the resistor noise, but compares

favorably with precision bipolar op amps.

The OPA627/637 is laser-trimmed for low offset voltage

and drift, so many circuits will not require external adjust-

ment. Figure 3 shows the optional connection of an external

potentiometer to adjust offset voltage. This adjustment should

not be used to compensate for offsets created elsewhere in a

system (such as in later amplification stages or in an A/D

converter) because this could introduce excessive tempera-

ture drift. Generally, the offset drift will change by approxi-

mately 4µV/°C for 1mV of change in the offset voltage due

to an offset adjustment (as shown on Figure 3).

CIRCUIT LAYOUT

As with any high speed, wide bandwidth circuit, careful

layout will ensure best performance. Make short, direct

interconnections and avoid stray wiring capacitance—espe-

cially at the input pins and feedback circuitry.

The case (TO-99 metal package only) is internally connected

to the negative power supply as it is with most common op

amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages

has no internal connection.

C₂

Power supply connections should be bypassed with good

high frequency capacitors positioned close to the op amp

pins. In most cases 0.1µF ceramic capacitors are adequate.

The OPA627/637 is capable of high output current (in

excess of 45mA). Applications with low impedance loads or

capacitive loads with fast transient signals demand large

currents from the power supplies. Larger bypass capacitors

such as 1µF solid tantalum capacitors may improve dynamic

performance in these applications.

R₂

C₁

–

OPA637

R₁

C₁= C_IN+ C_STRAY

R₁C₁

C₂

R₂

FIGURE 2. Circuits with Noise Gain Equal to or Greater than

Five May Use the OPA637.

+V_S

100kΩ

NOISE PERFORMANCE

10kΩ to 1MΩ

Potentiometer

(100kΩ preferred)

Some bipolar op amps may provide lower voltage noise

performance, but both voltage noise and bias current noise

contribute to the total noise of a system. The OPA627/637

is unique in providing very low voltage noise and very low

current noise. This provides optimum noise performance

over a wide range of sources, including reactive source

impedances. This can be seen in the performance curve

showing the noise of a source resistor combined with the

noise of an OPA627. Above a 2kΩ source resistance, the op

–

OPA627/637

±10mV Typical

Trim Range

–V_S

FIGURE 3. Optional Offset Voltage Trim Circuit.

Non-inverting

Buffer

–

OPA627

Out

OPA627

TO-99 Bottom View

Inverting

OPA627

–

Out

Board Layout for Input Guarding:

Guard top and bottom of board.

Alternate—use Teflon^®standoff for sen-

sitive input pins.

No Internal Connection

Teflon^®E.I. du Pont de Nemours & Co.

To Guard Drive

FIGURE 4. Connection of Input Guard for Lowest I_B.

OPA627, 637

INPUT BIAS CURRENT

takes approximately 500ns. When the output is driven into

the positive limit, recovery takes approximately 6µs. Output

recovery of the OPA627 can be improved using the output

clamp circuit shown in Figure 5. Diodes at the inverting

input prevent degradation of input bias current.

Difet fabrication of the OPA627/637 provides very low

input bias current. Since the gate current of a FET doubles

approximately every 10°C, to achieve lowest input bias

current, the die temperature should be kept as low as pos-

sible. The high speed and therefore higher quiescent current

of the OPA627/637 can lead to higher chip temperature. A

simple press-on heat sink such as the Burr-Brown model

807HS (TO-99 metal package) can reduce chip temperature

by approximately 15°C, lowering the I_Bto one-third its

warmed-up value. The 807HS heat sink can also reduce low-

frequency voltage noise caused by air currents and thermo-

electric effects. See the data sheet on the 807HS for details.

+V_S

5kΩ

(2)

HP 5082-2811

Diode Bridge

ZD₁

Temperature rise in the plastic DIP and SOIC packages can

be minimized by soldering the device to the circuit board.

Wide copper traces will also help dissipate heat.

BB: PWS740-3

1kΩ

ZD₁: 10V IN961

5kΩ

The OPA627/637 may also be operated at reduced power

supply voltage to minimize power dissipation and tempera-

ture rise. Using ±5V power supplies reduces power dissipa-

tion to one-third of that at ±15V. This reduces the I_Bof TO-

99 metal package devices to approximately one-fourth the

value at ±15V.

R_F

V_I

–

–V_S

V_O

Clamps output

at V_O= ±11.5V

R_I

OPA627

Leakage currents between printed circuit board traces can

easily exceed the input bias current of the OPA627/637. A

circuit board “guard” pattern (Figure 4) reduces leakage

effects. By surrounding critical high impedance input cir-

cuitry with a low impedance circuit connection at the same

potential, leakage current will flow harmlessly to the low-

impedance node. The case (TO-99 metal package only) is

internally connected to –V_S.

FIGURE 5. Clamp Circuit for Improved Overload Recovery.

CAPACITIVE LOADS

As with any high-speed op amp, best dynamic performance

can be achieved by minimizing the capacitive load. Since a

load capacitance presents a decreasing impedance at higher

frequency, a load capacitance which is easily driven by a

slow op amp can cause a high-speed op amp to perform

poorly. See the typical curves showing settling times as a

function of capacitive load. The lower bandwidth of the

OPA627 makes it the better choice for driving large capaci-

tive loads. Figure 6 shows a circuit for driving very large

load capacitance. This circuit’s two-pole response can also

be used to sharply limit system bandwidth. This is often

useful in reducing the noise of systems which do not require

the full bandwidth of the OPA627.

Input bias current may also be degraded by improper han-

dling or cleaning. Contamination from handling parts and

circuit boards may be removed with cleaning solvents and

deionized water. Each rinsing operation should be followed

by a 30-minute bake at 85°C.

Many FET-input op amps exhibit large changes in input

bias current with changes in input voltage. Input stage

cascode circuitry makes the input bias current of the

OPA627/637 virtually constant with wide common-mode

voltage changes. This is ideal for accurate high input-

impedance buffer applications.

R_F

1kΩ

PHASE-REVERSAL PROTECTION

The OPA627/637 has internal phase-reversal protection.

Many FET-input op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This

is most often encountered in non-inverting circuits when the

input is driven below –12V, causing the output to reverse

into the positive rail. The input circuitry of the OPA627/637

does not induce phase reversal with excessive common-

mode voltage, so the output limits into the appropriate rail.

200pF

G = +1

BW ≥ 1MHz

C_F

R_O

20Ω

–

C_L

5nF

OPA627

R_F

R₁

G = 1+

For Approximate Butterworth Response:

Optional Gain

Gain > 1

2 R_OC_L

R_F>> R_O

C_F

R_F

OUTPUT OVERLOAD

When the inputs to the OPA627/637 are overdriven, the

output voltage of the OPA627/637 smoothly limits at ap-

proximately 2.5V from the positive and negative power

supplies. If driven to the negative swing limit, recovery

f_–3dB

2π √ R_FR_OC_FC_L

FIGURE 6. Driving Large Capacitive Loads.

OPA627, 637

INPUT PROTECTION

Sometimes input protection is required on I/V converters of

inverting amplifiers (Figure 7b). Although in normal opera-

tion, the voltage at the summing junction will be near zero

(equal to the offset voltage of the amplifier), large input

transients may cause this node to exceed 2V beyond the

power supplies. In this case, the summing junction should

be protected with diode clamps connected to ground. Even

with the low voltage present at the summing junction,

common signal diodes may have excessive leakage current.

Since the reverse voltage on these diodes is clamped, a

diode-connected signal transistor can be used as an inexpen-

sive low leakage diode (Figure 7b).

The inputs of the OPA627/637 are protected for voltages

between +V_S+ 2V and –V_S– 2V. If the input voltage can

exceed these limits, the amplifier should be protected. The

diode clamps shown in Figure 7a will prevent the input

voltage from exceeding one forward diode voltage drop

beyond the power supplies—well within the safe limits. If

the input source can deliver current in excess of the maxi-

mum forward current of the protection diodes, use a series

resistor, R_S, to limit the current. Be aware that adding

resistance to the input will increase noise. The 4nV/√Hz

theoretical thermal noise of a 1kΩ resistor will add to the

4.5nV/√Hz noise of the OPA627/637 (by the square-root of

the sum of the squares), producing a total noise of 6nV/√Hz.

Resistors below 100Ω add negligible noise.

+V_S

Leakage current in the protection diodes can increase the

total input bias current of the circuit. The specified maxi-

mum leakage current for commonly used diodes such as the

1N4148 is approximately 25nA—more than a thousand

times larger than the input bias current of the OPA627/637.

Leakage current of these diodes is typically much lower and

may be adequate in many applications. Light falling on the

junction of the protection diodes can dramatically increase

leakage current, so common glass-packaged diodes should

be shielded from ambient light. Very low leakage can be

achieved by using a diode-connected FET as shown. The

2N4117A is specified at 1pA and its metal case shields the

junction from light.

–

V_O

OPA627

D: IN4148 — 25nA Leakage

2N4117A — 1pA Leakage

Siliconix

Optional R_S

–V_S

(a)

I_IN

–

V_O

OPA627

D: 2N3904

(b)

FIGURE 7. Input Protection Circuits.

SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE

(A)

(B)

FPO

When used as a unity-gain buffer, large common-mode input voltage steps

produce transient variations in input-stage currents. This causes the rising

edge to be slower and falling edges to be faster than nominal slew rates

observed in higher-gain circuits.

G = 1

–

OPA627

FIGURE 8. OPA627 Dynamic Performance, G = +1.

OPA627, 637

LARGE SIGNAL RESPONSE

+10

(C)

(D)

–10

6pF⁽¹⁾

NOTE: (1) Optimum value will

depend on circuit board lay-

out and stray capacitance at

the inverting input.

When driven with a very fast input step (left), common-mode

transients cause a slight variation in input stage currents which

will reduce output slew rate. If the input step slew rate is reduced

(right), output slew rate will increase slightly.

2kΩ

G = –1

V_OUT

–

2kΩ

OPA627

FIGURE 9. OPA627 Dynamic Performance, G = –1.

OPA637

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

+10

+100

(E)

(F)

FPO

–10

–100

4pF⁽¹⁾

2kΩ

G = 5

V_OUT

–

OPA637

500Ω

NOTE: (1) Optimum value will depend on circuit

board layout and capacitance at inverting input.

FIGURE 10. OPA637 Dynamic Response, G = 5.

OPA627, 637

Error Out

R_I^/

2kΩ

OPA627

OPA637

C_F

R_I, R₁

C_F

Error Band

(0.01%)

2kΩ

6pF

±0.5mV

500Ω

4pF

±0.2mV

HP-

5082-

2835

2kΩ

+15V

R_I

High Quality

–

NOTE: C_Fis selected for best settling time performance

depending on test fixture layout. Once optimum value is

determined, a fixed capacitor may be used.

±5V

Out

Pulse Generator

51Ω

–15V

FIGURE 11. Settling Time and Slew Rate Test Circuit.

Gain = 100

≈

CMRR 116dB

OPA637

–In

–

≈

Bandwidth 1MHz

R_F

5kΩ

25kΩ

Input Common-Mode

Range = ±5V

INA105

Differential

Amplifier

R_G

101Ω

3pF

Output

–

R_F

5kΩ

25kΩ

–

+In

OPA637

Differential Voltage Gain = 1 + 2R_F/R_G

FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100.

Gain = 1000

≈

CMRR 116dB

OPA637

–In

–

≈

Bandwidth 400kHz

R_F

5kΩ

10kΩ

100kΩ

Input Common-Mode

Range = ±10V

INA106

Differential

Amplifier

R_G

101Ω

3pF

Output

–

R_F

5kΩ

10kΩ

100kΩ

–

+In

OPA637

Differential Voltage Gain = (1 + 2R_F/R_G) • 10

FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000.

This composite amplifier uses the OPA603 current-feedback op amp to

provide extended bandwidth and slew rate at high closed-loop gain. The

feedback loop is closed around the composite amp, preserving the

precision input characteristics of the OPA627/637. Use separate power

supply bypass capacitors for each op amp.

R₂

–

A₁

–

*Minimize capacitance at this node.

V_I

V_O

GAIN

(V/V)

A₁

OP AMP

R₁

(Ω)

R₂

(kΩ)

R₃

R₄

–3dB

SLEW RATE

OPA603

_L≥ 150Ω

for ±10V Out

(Ω)

(kΩ) (MHz)

(V/µs)

R₁

100

1000

OPA627

OPA637

50.5⁽¹⁾4.99

49.9 4.99

700

500

R₃

R₄

NOTE: (1) Closest 1/2% value.

FIGURE 14. Composite Amplifier for Wide Bandwidth.

OPA627, 637

OPA637AU相关文章

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OPA637AU产品参数

型号:	OPA637AU
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	BURR-BROWN CORP
Reach Compliance Code：	unknown
风险等级：	5.69
Is Samacsys：	N
放大器类型：	OPERATIONAL AMPLIFIER
架构：	VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)：	0.002 µA
25C 时的最大偏置电流 (IIB)：	0.00001 µA
最小共模抑制比：	100 dB
标称共模抑制比：	110 dB
频率补偿：	YES (AVCL>=5)
最大输入失调电压：	500 µV
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0
低-偏置：	YES
低-失调：	YES
负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
电源：	+-15 V
认证状态：	Not Qualified
最小摆率：	100 V/us
标称压摆率：	135 V/us
子类别：	Operational Amplifier
最大压摆率：	7.5 mA
供电电压上限：	18 V
标称供电电压 (Vsup)：	15 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
标称均一增益带宽：	80000 kHz
最小电压增益：	200000
Base Number Matches：	1

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