OPA691ID各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

OPA691

O

P

A

6

9

1

O

P

A

6

9

1

SBOS226A – DECEMBER 2001– REVISED SEPTEMBER 2002

Wideband, Current Feedback

OPERATIONAL AMPLIFIER With Disable

FEATURES

APPLICATIONS

●

FLEXIBLE SUPPLY RANGE:

● xDSL LINE DRIVER

+5V to +12V Single-Supply

● BROADBAND VIDEO BUFFERS

● HIGH-SPEED IMAGING CHANNELS

● PORTABLE INSTRUMENTS

● ADC BUFFERS

● ACTIVE FILTERS

● WIDEBAND INVERTING SUMMING

● HIGH SFDR IF AMPLIFIER

±2.5V to

±6V Dual-Supply

●

UNITY-GAIN STABLE: 280MHz (G = 1)

● HIGH OUTPUT CURRENT: 190mA

● OUTPUT VOLTAGE SWING: ±4.0V

● HIGH SLEW RATE: 2100V/µs

φ

● LOW dG/d : 0.07%/0.02°

● LOW SUPPLY CURRENT: 5.1mA

● LOW DISABLED CURRENT: 150µA

●

WIDEBAND +5V OPERATION: 190MHz (G = +2)

ensures lower maximum supply current than competing

products. System power may be further reduced by using the

optional disable control pin. Leaving this disable pin open, or

holding it HIGH, gives normal operation. If pulled LOW, the

OPA691 supply current drops to less than 150µA while the

output goes into a high impedance state. This feature may be

used for power savings.

DESCRIPTION

The OPA691 sets a new level of performance for broadband

current feedback op amps. Operating on a very low 5.1mA

supply current, the OPA691 offers a slew rate and output

power normally associated with a much higher supply cur-

rent. A new output stage architecture delivers a high output

current with minimal voltage headroom and crossover distor-

tion. This gives exceptional single-supply operation. Using a

single +5V supply, the OPA691 can deliver a 1V to 4V output

swing with over 150mA drive current and 190MHz band-

width. This combination of features makes the OPA691 an

ideal RGB line driver or single-supply Analog-to-Digital Con-

verter (ADC) input driver.

OPA691 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

Voltage Feedback

Current Feedback

Fixed Gain

OPA690

OPA681

OPA692

OPA2690

OPA2691

OPA3690

OPA3691

OPA3692

The OPA691’s low 5.1mA supply current is precisely trimmed

at 25°C. This trim, along with low drift over-temperature,

+5V

DIS

50Ω

V_O= –(V₁+ V₂+ V₃+ V₄+ V₅)

50Ω

OPA691

V₁

RG-58

50Ω

V₂

50Ω

30Ω

V₃

100Ω

100MHz, –1dB Compression = 15dBm

50Ω

V₄

50Ω

–5V

V₅

200MHz RF Summing Amplifier

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

Power Supply .............................................................................. ±6.5VDC

Internal Power Dissipation⁽²⁾............................ See Thermal Information

Differential Input Voltage .................................................................. ±1.2V

Input Voltage Range............................................................................ ±V_S

Storage Temperature Range: ID, IDBV .........................–40°C to +125°C

Lead Temperature (soldering, 10s).............................................. +300°C

Junction Temperature (T_J) ........................................................... +175°C

ESD Performance:

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

HBM .............................................................................................. 2000V

CDM .............................................................................................. 1500V

ESD damage can range from subtle performance degradation

tocompletedevicefailure. Precisionintegratedcircuitsmaybe

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

NOTES:: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability. (2) Packages must be derated based on specified θ_JA

.

Maximum T_Jmust be observed.

PACKAGE/ORDERING INFORMATION

SPECIFIED

PACKAGE

DESIGNATOR⁽¹⁾

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

OPA691ID

SO-8

D

"

–40°C to +85°C

OPA691

OPA691ID

OPA691IDR

Rails, 100

"

OAFI

"

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 3000

OPA691IDBV

SOT23-6

DBV

–40°C to +85°C

OPA691IDBVT

OPA691IDBVR

"

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PIN CONFIGURATION

Top View

SOT

Top View

SO

Output

1

2

3

6

5

4

+V_S

–V_S

DIS

NC

Inverting Input

Noninverting Input

–V_S

1

2

3

4

8

7

6

5

DIS

Noninverting Input

Inverting Input

+V_S

Output

NC

6

5

4

NC = No Connection

OAFI

1

2

3

Pin Orientation/Package Marking

OPA691

2

SBOS226A

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±5V

Boldface limits are tested at +25°C.

R_F= 402Ω, R_L= 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.

OPA691ID, IDBV

TYP

MIN/MAX OVER-TEMPERATURE

0°C to

–40°C to

MIN/

TEST

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

MAX LEVEL⁽³⁾

AC PERFORMANCE (see Figure 1)

Small-Signal Bandwidth (V_O= 0.5Vp-p)

G = +1, R_F= 453Ω

G = +2, R_F= 402Ω

G = +5, R_F= 261Ω

G = +10, R_F= 180Ω

G = +2, V_O= 0.5Vp-p

280

225

210

200

90

0.2

200

2100

1.6

1.9

12

MHz

dB

MHz

V/µs

ns

typ

min

typ

C

B

C

B

C

B

C

200

190

180

typ

Bandwidth for 0.1dB Gain Flatness

Peaking at a Gain of +1

Large-Signal Bandwidth

Slew Rate

40

1

35

1.5

20

2

min

max

typ

min

typ

R

_F= 453, V_O= 0.5Vp-p

G = +2, V_O= 5Vp-p

G = +2, 4V Step

1400

1375

1350

Rise-and-Fall Time

G = +2, V_O= 0.5V Step

G = +2, 5V Step

G = +2, V_O= 2V Step

ns

Settling Time to 0.02%

0.1%

8

Harmonic Distortion

2nd-Harmonic

G = +2, f = 5MHz, V_O= 2Vp-p

R_L= 100Ω

–70

–79

–74

–93

1.7

12

15

0.07

0.17

0.02

0.07

–63

–70

–72

–87

2.5

14

–60

–67

–70

–82

2.9

15

–58

–65

–68

–78

3.1

15

dBc

max

typ

B

C

R

_L≥ 500Ω

R_L= 100Ω

_L≥ 500Ω

3rd-Harmonic

R

dBc

Input Voltage Noise

f > 1MHz

nV/√HZ

pA/√HZ

%

deg

Noninverting Input Current Noise

Inverting Input Current Noise

Differential Gain

17

18

19

G = +2, NTSC, V_O= 1.4Vp, R_L= 150Ω

R_L= 37.5Ω

G = +2, NTSC, V_O= 1.4Vp, R_L= 150Ω

R_L= 37.5Ω

typ

Differential Phase

deg

DC PERFORMANCE⁽⁴⁾

Open-Loop Transimpedance Gain (Z_OL

Input Offset Voltage

Average Offset Voltage Drift

Noninverting Input Bias Current

Average Noninverting Input Bias Current Drift

Inverting Input Bias Current

)

V_O= 0V, R_L= 100Ω

V_CM= 0V

225

±0.5

125

±2.5

110

±3.2

±12

+43

–300

±30

±90

100

±3.9

±20

+45

–300

±40

kΩ

mV

µV/°C

µA

nA/°C

µA

nA°/C

min

max

A

B

A

B

A

B

V_CM= 0V

+15

+35

V

_CM= 0V

V_CM= 0V

±5

±25

Average Inverting Input Bias Current Drift

±200

INPUT

Common-Mode Input Range⁽⁵⁾

Common-Mode Rejection

Noninverting Input Impedance

Inverting Input Resistance (R_I)

±3.5

56

100 || 2

35

±3.4

52

±3.3

51

±3.2

50

V

dB

kΩ || pF

Ω

min

typ

A

C

V_CM= 0V

Open-Loop

typ

OUTPUT

Voltage Output Swing

No Load

100Ω Load

V_O= 0

±4.0

±3.9

+190

–190

±250

0.03

±3.8

±3.7

+160

–160

±3.7

±3.6

+140

–140

±3.6

±3.3

+100

–100

V

mA

Ω

min

typ

A

C

Current Output, Sourcing

Current Output, Sinking

Short-Circuit Current

V_O= 0

V

_O= 0

Closed-Loop Output Impedance

G = +2, f = 100kHz

typ

DISABLE (Disabled LOW)

Power-Down Supply Current (+V_S)

Disable Time

Enable Time

Off Isolation

Output Capacitance in Disable

Turn On Glitch

Turn Off Glitch

Enable Voltage

Disable Voltage

V_DIS= 0

V_IN= 1V

–150

400

25

70

4

±50

±20

3.3

1.8

75

–300

–350

–400

µA

ns

dB

pF

mV

V

max

typ

min

max

A

C

A

G = +2, 5MHz

G = +2, R_L= 150Ω, V_IN= 0

3.5

1.7

130

3.6

1.6

150

3.7

1.5

160

V

µA

Control Pin Input Bias Current (DIS)

V_DIS= 0

POWER SUPPLY

Specified Operating Voltage

Maximum Operating Voltage Range

Max Quiescent Current

Min Quiescent Current

Power-Supply Rejection Ratio (–PSRR)

±5

V

mA

dB

typ

max

min

C

A

±6

5.3

4.9

52

±6

5.5

4.7

50

±6

5.7

4.5

49

V_S= ±5V

Input Referred

5.1

58

TEMPERATURE RANGE

Specification: D, DBV

–40 to +85

°C

typ

C

Thermal Resistance, θ_JA

Junction-to-Ambient

D

SO-8

125

150

°C/W

typ

C

DBV SOT23-6

NOTES: (1) Junction temperature = ambient for 25°C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +10°C

at high temperature limit for over-temperature specifications. (3) Test levels: (A) 100% tested at 25°C. Over-temperature limits by characterization and simulation.

(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V_CMis the input common-mode

voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.

OPA691

SBOS226A

3

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= +5V

Bolace limits are tested at +25°C.

R_F= 453Ω, R_L= 100Ω to V_S/2, and G = +2, (see Figure 2 for AC performance only), unless otherwise noted.

OPA691ID, IDBV

TYP

MIN/MAX OVER-TEMPERATURE

0

°

C to

–40

°

C to

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

AC PERFORMANCE (see Figure 2)

Small-Signal Bandwidth (V_O= 0.5Vp-p)

G = +1, R_F= 499Ω

G = +2, R_F= 453Ω

G = +5, R_F= 340Ω

G = +10, R_F= 180Ω

G = +2, V_O< 0.5Vp-p

_F= 649Ω, V_O< 0.5Vp-p

G = +2, V_O= 2Vp-p

G = +2, 2V Step

G = +2, V_O= 0.5V Step

G = +2, V_O= 2V Step

210

190

180

155

90

0.2

210

850

2.0

2.3

14

MHz

dB

MHz

V/µs

ns

typ

min

typ

C

B

C

B

C

B

C

168

160

140

typ

Bandwidth for 0.1dB Gain Flatness

Peaking at a Gain of +1

Large-Signal Bandwidth

Slew Rate

40

1

30

2.5

25

3.0

min

max

typ

min

typ

R

600

575

550

Rise-and-Fall Time

ns

Settling Time to 0.02%

0.1%

10

Harmonic Distortion

2nd-Harmonic

G = +2, f = 5MHz, V_O= 2Vp-p

R_L= 100Ω to V_S/2

–66

–73

–71

–77

1.7

12

–58

–65

–68

–72

2.5

14

–57

–63

–67

–70

2.9

15

–56

–62

–65

–69

3.1

15

dBc

max

typ

B

R_L≥ 500Ω to V_S/2

3rd-Harmonic

R_L= 100Ω to V_S/2

R_L≥ 500Ω to V_S/2

dBc

Input Voltage Noise

Noninverting Input Current Noise

Inverting Input Current Noise

f > 1MHz

nV/√Hz

pA/√Hz

typ

15

17

18

19

DC PERFORMANCE⁽⁴⁾

Open-Loop Transimpedance Gain (Z_OL

Input Offset Voltage

Average Offset Voltage Drift

Noninverting Input Bias Current

Average Noninverting Input Bias Current Drift

Inverting Input Bias Current

)

V_O= V_S/2, R_L= 100Ω to V_S/2

200

±0.5

100

±3

90

±3.6

±12

+46

–250

±25

80

±4.3

±20

+56

–250

±35

kΩ

mV

µV/°C

µA

nA/°C

µA

nA/°C

min

max

A

B

A

B

A

B

V_CM= 2.5V

V

_CM= 2.5V

+20

+40

V_CM= 2.5V

V

_CM= 2.5V

±5

±20

Average Inverting Input Bias Current Drift

±112

±250

INPUT

Least Positive Input Voltage⁽⁵⁾

Most Positive Input Voltage⁽⁵⁾

Common-Mode Rejection Ratio (CMRR)

Noninverting Input Impedance

Inverting Input Resistance (R_I)

1.5

3.5

54

100 || 2

38

1.6

3.4

50

1.7

3.3

49

1.8

3.2

48

V

dB

kΩ || pF

Ω

max

min

typ

A

C

V_CM= V_S/2

Open-Loop

typ

OUTPUT

Most Positive Output Voltage

No Load

R_L= 100Ω to V_S/2

No Load

4

3.9

1

1.1

+160

–160

250

0.03

3.8

3.7

1.2

1.3

+120

–120

3.7

3.6

1.3

1.4

+100

–100

3.5

3.4

1.5

1.6

+80

–80

V

min

max

min

typ

A

C

Least Positive Output Voltage

R_L= 100Ω to V_S/2

V

Current Output, Sourcing

Current Output, Sinking

Short-Circuit Current

V

_O= V_S/2

V_O= V_S/2

_O= V_S/2

mA

Ω

V

Closed-Loop Output Impedance

G = +2, f = 100kHz

typ

DISABLE (Disabled LOW)

Power-Down Supply Current (+V_S)

Off Isolation

Output Capacitance in Disable

Turn On Glitch

Turn Off Glitch

Enable Voltage

Disable Voltage

Control Pin Input Bias Current (DIS)

V_DIS= 0

G = +2, 5MHz

–150

65

4

±50

±20

3.3

1.8

75

–300

–350

–400

µA

dB

pF

mV

V

max

typ

min

max

typ

A

C

A

C

G = +2, R_L= 150Ω, V_IN= V_S/2

3.5

1.7

130

3.6

1.6

150

3.7

1.5

160

V

µA

V_DIS= 0

POWER SUPPLY

Specified Single-Supply Operating Voltage

Max Single-Supply Operating Voltage

Max Quiescent Current

Min Quiescent Current

Power-Supply Rejection Ratio (–PSRR)

5

V

mA

dB

typ

max

min

typ

C

A

C

12

4.8

4.1

12

5.0

4.0

12

5.2

3.8

V

_S= +5V

4.5

55

Input Referred

TEMPERATURE RANGE

Specification: D, DBV

–40 to +85

°C

typ

C

Thermal Resistance, θ_JA

Junction-to-Ambient

D

DBV

SO-8

SOT23-6

125

150

°C/W

typ

C

NOTES: (3) Test levels: (A) 100% tested at 25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.

(C) Typical value only for information. (1) Junction temperature = ambient for 25°C specifications. (2) Junction temperature = ambient at low temperature limit: junction

temperature = ambient +10°C at high temperature limit for over-temperature specifications. (3) Test levels: (A) 100% tested at 25°C. Over-temperature limits by

characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node.

V_CMis the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.

OPA691

4

SBOS226A

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V

G = +2, R_F= 402Ω, and R_L= 100Ω, unless otherwise noted (see Figure 1).

SMALL-SIGNAL FREQUENCY RESPONSE

LARGE-SIGNAL FREQUENCY RESPONSE

G = +2, R_L= 100Ω

1

0

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

G = +1, R_F= 453Ω

G = +2,

2Vp-p

1Vp-p

R_F= 402Ω

–1

–2

–3

–4

–5

–6

–7

–8

G = +5, R_F= 261Ω

G = +10, R_F= 180Ω

4Vp-p

7Vp-p

V_O= 0.5Vp-p

0

125MHz

Frequency (25MHz/div)

250MHz

0

125MHz

250MHz

Frequency (25MHz/div)

SMALL-SIGNAL PULSE RESPONSE

LARGE-SIGNAL PULSE RESPONSE

+4

+3

+2

+1

0

+400

+300

+200

+100

0

G = +2

_O= 0.5Vp-p

G = +2

V_O= 5Vp-p

V

–1

–2

–3

–4

–100

–200

–300

–400

Time (5ns/div)

DISABLED FEEDTHROUGH vs FREQUENCY

V_DIS= 0

COMPOSITE VIDEO dG/dP

No Pull-Down

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

0.2

0.18

0.16

0.14

0.12

0.1

+5

Video

In

Video

Loads

With 1.3kΩ Pull-Down

OPA691

402Ω

dG

402Ω

Optional 1.3kΩ

–5

Pull-Down

dG

0.08

0.06

0.04

0.02

0

Reverse

dP

Forward

0.3

1

10

Frequency (MHz)

100

1

2

3

4

Number of 150Ω Loads

OPA691

SBOS226A

5

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

G = +2, R_F= 402Ω, and R_L= 100Ω, unless otherwise noted (see Figure 1).

HARMONIC DISTORTION vs LOAD RESISTANCE

HARMONIC DISTORTION vs SUPPLY VOLTAGE

V_O= 2Vp-p

–60

–65

–70

–75

–80

–85

–90

–95

–100

–60

–65

–70

–75

–80

–85

V_O= 2Vp-p

f = 5MHz

R_L= 100Ω

f = 5MHz

2nd-Harmonic

3rd-Harmonic

100

1000

2.5

3

3.5

4

4.5

5

5.5

6

Load Resistance (Ω)

Supply Voltage (V)

HARMONIC DISTORTION vs FREQUENCY

HARMONIC DISTORTION vs OUTPUT VOLTAGE

–50

–60

–65

–70

–75

–80

–85

dBc = dB Below Carrier

R_L= 100Ω

f = 5MHz

2nd-Harmonic

V_O= 2Vp-p

_L= 100Ω

2nd-Harmonic

R

–70

3rd-Harmonic

–80

–90

–100

0.1

1

10

20

0.1

1

5

Frequency (MHz)

Output Voltage Swing (Vp-p)

HARMONIC DISTORTION vs INVERTING GAIN

HARMONIC DISTORTION vs NONINVERTING GAIN

V_O= 2Vp-p

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

V_O= 2Vp-p

_L= 100Ω

f = 5MHz

_F= 402Ω

R_L= 100Ω

R

f = 5MHz

R

2nd-Harmonic

3rd-Harmonic

2nd-Harmonic

3rd-Harmonic

1

10

1

10

Inverting Gain (V/V)

Gain (V/V)

OPA691

6

SBOS226A

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

G = +2, R_F= 402Ω, and R_L= 100Ω, unless otherwise noted (see Figure 1).

2-TONE, 3RD-ORDER

INPUT VOLTAGE AND CURRENT NOISE DENSITY

INTERMODULATION SPURIOUS

100

10

1

–30

–40

–50

–60

–70

–80

–90

dBc = dB below carriers

50MHz

Inverting Input Current Noise (15pA/√Hz)

20MHz

10MHz

Noninverting Input Current Noise (12pA/√Hz)

Voltage Noise (1.7nV/√Hz)

Load Power at Matched 50Ω Load

100

1k

10k

100k

1M

10M

–8

–6

–4

–2

0

2

4

6

8

10

Frequency (Hz)

Single-Tone Load Power (dBm)

RECOMMENDED R_Svs CAPACITIVE LOAD

FREQUENCY RESPONSE vs CAPACITIVE LOAD

70

60

50

40

30

20

10

0

9

6

C_L= 10pF

3

C_L= 22pF

0

C_L= 47pF

V_IN

R_S

C_L

V_O

–3

–6

–9

OPA691

402Ω

1kΩ

402Ω

C_L= 100pF

1kΩ is optional.

1

10

100

1k

0

125MHz

Frequency (25MHz/div)

250MHz

Capacitive Load (pF)

OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE

CMRR AND PSRR vs FREQUENCY

+PSRR

65

60

55

50

45

40

35

30

25

20

120

100

80

60

40

20

0

–40

|Z_OL

|

CMRR

Z_OL

–80

–PSRR

–120

–160

–200

–240

1k

10k

100k

1M

10M

100M

10k

100k

1M

10M

100M

1G

Frequency (Hz)

OPA691

SBOS226A

7

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

G = +2, R_F= 402Ω, and R_L= 100Ω, unless otherwise noted (see Figure 1).

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

10

8

250

200

150

100

50

5

4

Output Current Limit

Sourcing Output Current

Sinking Output Current

1W Internal

Power Limit

3

2

1

6

0

25Ω

Load Line

–1

–2

–3

–4

–5

4

Quiescent Supply Current

50Ω Load Line

100Ω Load Line

2

1W Internal

Power Limit

Output Current Limit

0

–50

–25

0

25

50

75

100

125

–300 –250 –200 –150 –100 –50

0

+50 +100 +150 +200 +250 +300

Ambient Temperature (°C)

I_O(mA)

CLOSED-LOOP OUTPUT IMPEDANCE

vs FREQUENCY

TYPICAL DC DRIFT OVER TEMPERATURE

2

40

10

1

+5

1.5

1

30

Noninverting Input Bias Current (I_B+

)

20

OPA691

50Ω

Z_O

0.5

0

10

402Ω

–5

0

402Ω

Inverting Input

Bias Current (I_B–

)

–0.5

–1

–10

–20

–30

–40

0.1

0.01

Input Offset

Voltage (V_OS

–1.5

–2

)

–50

–25

0

25

50

75

100

125

10k

100k

1M

10M

100M

Ambient Temperature (°C)

Frequency (Hz)

LARGE-SIGNAL DISABLE/ENABLE RESPONSE

V_DIS

DISABLE/ENABLE GLITCH

6.0

4.0

2.0

0

6.0

4.0

2.0

0

V_DIS

2.0

1.6

1.2

0.8

0.4

0

30

20

Output Voltage

(0V Input)

10

0

–10

–20

–30

V_IN= +1V

V_IN= 0V

Time (200ns/div)

Time (20ns/div)

OPA691

8

SBOS226A

www.ti.com

TYPICAL CHARACTERISTICS: V_S= +5V

G = +2, R_F= 453Ω, and R_L= 100Ω to +2.5V, unless otherwise noted (see Figure 2).

SMALL-SIGNAL FREQUENCY RESPONSE

LARGE-SIGNAL FREQUENCY RESPONSE

V_O= 0.5Vp-p

1

0

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

G = +1,

R_F= 499Ω

–1

–2

–3

–4

–5

–6

–7

–8

G = +2,

R_F= 453Ω

G = +5,

R_F= 340Ω

V_O= 2Vp-p

G = +10,

V_O= 1Vp-p

G = +2

R_F= 180Ω

R_L= 100Ω to 2.5V

V_O= 0.5Vp-p

0

125MHz

250MHz

0

125MHz

250MHz

Frequency (25MHz/div)

SMALL-SIGNAL PULSE RESPONSE

LARGE-SIGNAL PULSE RESPONSE

4.1

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

G = +2

_O= 0.5Vp-p

G = +2

_O= 2Vp-p

V

Time (5ns/div)

RECOMMENDED R_Svs CAPACITIVE LOAD

FREQUENCY RESPONSE vs CAPACITIVE LOAD

60

50

40

30

20

10

0

9

6

C_L= 10pF

3

C_L= 47pF

0

C_L= 22pF

+5V

806Ω

–3

–6

–9

0.1µF

57.6Ω

V

I

V

O

OPA691

C_L= 100pF

R

S

C

1kΩ

L

453Ω

0.1µF

1kΩ is optional.

1

10

100

0

125MHz

Frequency (25MHz/div)

250MHz

Capacitive Load (pF)

OPA691

SBOS226A

9

www.ti.com

TYPICAL CHARACTERISTICS: V_S= +5V (Cont.)

G = +2, R_F= 453Ω, and R_L= 100Ω to +2.5V, unless otherwise noted (see Figure 2).

HARMONIC DISTORTION vs FREQUENCY

HARMONIC DISTORTION vs LOAD RESISTANCE

–50

–60

–70

–80

–90

–60

–65

–70

–75

–80

V_O= 2Vp-p

f = 5MHz

V_O= 2Vp-p

_L= 100Ω to 2.5V

R

2nd-Harmonic

3rd-Harmonic

0.1

1

10

20

100

1000

Frequency (MHz)

Resistance (Ω)

2-TONE, 3RD-ORDER

INTERMODULATION SPURIOUS

HARMONIC DISTORTION vs OUTPUT VOLTAGE

–30

–40

–50

–60

–70

–80

–90

–100

–60

–65

–70

–75

–80

dBc = dB below carriers

50MHz

R_L= 100Ω to 2.5V

f = 5MHz

2nd-Harmonic

20MHz

10MHz

3rd-Harmonic

Load Power at Matched 50Ω Load

–6 –4 –2

Single-Tone Load Power (dBm)

–14

–12

–10

–8

0

2

0.1

1

3

Output Voltage Swing (Vp-p)

OPA691

10

SBOS226A

www.ti.com

pins. In practical PC board layouts, this optional added

capacitor will typically improve the 2nd-harmonic distortion

performance by 3dB to 6dB.

APPLICATIONS INFORMATION

WIDEBAND CURRENT FEEDBACK OPERATION

The OPA691 gives the exceptional AC performance of a

wideband current feedback op amp with a highly linear, high

power output stage. Requiring only 5.1mA quiescent current,

the OPA691 will swing to within 1V of either supply rail and

deliver in excess of 160mA at room temperature. This low

output headroom requirement, along with supply voltage

independent biasing, gives remarkable single (+5V) supply

operation. The OPA691 will deliver greater than 200MHz

bandwidth driving a 2Vp-p output into 100Ω on a single +5V

supply. Previous boosted output stage amplifiers have typi-

cally suffered from very poor crossover distortion as the

output current goes through zero. The OPA691 achieves a

comparable power gain with much better linearity. The pri-

mary advantage of a current feedback op amp over a voltage

feedback op amp is that AC performance (bandwidth and

distortion) is relatively independent of signal gain. For similar

AC performance at low gains, with improved DC accuracy,

consider the high slew rate, unity-gain stable, voltage feed-

back OPA690.

Figure 2 shows the AC-coupled, gain of +2, single-supply

circuit configuration used as the basis of the +5V Electrical

Characteristic tables and Typical Characteristic curves.

Though not a “rail-to-rail” design, the OPA691 requires mini-

mal input and output voltage headroom compared to other

very wideband current feedback op amps. It will deliver a

3Vp-p output swing on a single +5V supply with greater than

150MHz bandwidth. The key requirement of broadband single-

supply operation is to maintain input and output signal

swings within the usable voltage ranges at both the input and

the output. The circuit of Figure 2 establishes an input

midpoint bias using a simple resistive divider from the +5V

supply (two 806Ω resistors). The input signal is then AC-

coupled into this midpoint voltage bias. The input voltage can

swing to within 1.5V of either supply pin, giving a 2Vp-p input

signal range centered between the supply pins. The input

impedance matching resistor (57.6Ω) used for testing is

adjusted to give a 50Ω input match when the parallel combi-

nation of the biasing divider network is included. The gain

resistor (R_G) is AC-coupled, giving the circuit a DC gain of

+1—which puts the input DC bias voltage (2.5V) on the

output as well. The feedback resistor value has been ad-

justed from the bipolar supply condition to re-optimize for a

flat frequency response in +5V, gain of +2, operation (see

Setting Resistor Values to Optimize Bandwidth). Again, on a

single +5V supply, the output voltage can swing to within 1V

of either supply pin while delivering more than 120mA output

current. A demanding 100Ω load to a mid-point bias is used

in this characterization circuit. The new output stage used in

the OPA691 can deliver large bipolar output currents into this

mid-point load with minimal crossover distortion, as shown by

the +5V supply, 3rd-harmonic distortion plots.

Figure 1 shows the DC-coupled, gain of +2, dual power-

supply circuit configuration used as the basis of the ±5V

Electrical Characteristic tables and Typical Characteristic

curves. For test purposes, the input impedance is set to 50Ω

with a resistor to ground and the output impedance is set to

50Ω with a series output resistor. Voltage swings reported in

the specifications are taken directly at the input and output

pins while load powers (dBm) are defined at a matched 50Ω

load. For the circuit of Figure 1, the total effective load will be

100Ω || 804Ω = 89Ω. The disable control line (DIS) is

typically left open to ensure normal amplifier operation. One

optional component is included in Figure 1. In addition to the

usual power-supply de-coupling capacitors to ground, a

0.1µF capacitor is included between the two power-supply

+5V

+V_S

+5V

+V_S

0.1µF

6.8µF

+

0.1µF

6.8µF

50Ω Source

806Ω

DIS

0.1µF

57.6Ω

DIS

V_O100Ω

50Ω Load

V_I

V_O50Ω

50Ω

V_I

OPA691

V_S/2

OPA691

R_F

453Ω

0.1µF

R_F

402Ω

R_G

453Ω

R_G

402Ω

0.1µF

6.8µF

0.1µF

+

–V_S

–5V

FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification

and Test Circuit.

FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-

tion and Test Circuit.

OPA691

SBOS226A

11

www.ti.com

SINGLE-SUPPLY ADC INTERFACE

the sum of R_F+ (R_I• NG) where R_Iis the impedance looking

into the inverting input from the summing junction (see the

Setting Resistor Values to Optimize Performance section).

Using 100Ω feedback (to get a signal gain of –2 from each

input to the output pin) requires an additional 30Ω in series

with the inverting input to increase the feedback impedance.

With this resistor added to the typical internal R_I= 35Ω, the

total feedback impedance is 100Ω + (65Ω • 6) = 490Ω, which

is equal to the required value to get a maximum bandwidth flat

frequency response for NG = 6. Tested performance shows

more than 200MHz small-signal bandwidth and a –1dBm

compression of 15dBm at the matched 50Ω load through

100MHz.

Most modern, high performance ADCs (such as the Texas

Instruments ADS8xx and ADS9xx series) operate on a single

+5V (or lower) power supply. It has been a considerable

challenge for single-supply op amps to deliver a low distor-

tion input signal at the ADC input for signal frequencies

exceeding 5MHz. The high slew rate, exceptional output

swing, and high linearity of the OPA691 make it an ideal

single-supply ADC driver. Figure 3 shows an example input

interface to a very high performance, 10-bit, 60MSPS CMOS

converter.

The OPA691 in the circuit of Figure 3 provides > 180MHz

bandwidth operating at a signal gain of +4 with a 2Vp-p

output swing. One of the primary advantages of the current

feedback internal architecture used in the OPA691 is that

high bandwidth can be maintained as the signal gain is

increased. The noninverting input bias voltage is referenced

to the midpoint of the ADC signal range by dividing off the top

and bottom of the internal ADC reference ladder. With the

gain resistor (R_G) AC-coupled, this bias voltage has a gain of

+1 to the output, centering the output voltage swing as well.

Tested performance at a 20MHz analog input frequency and

a 60MSPS clock rate on the converter gives > 58dBc SFDR.

WIDEBAND VIDEO MULTIPLEXING

One common application for video speed amplifiers which

include a disable pin is to wire multiple amplifier outputs

together, then select which one of several possible video

inputs to source onto a single line. This simple “Wired-OR

Video Multiplexer” can be easily implemented using the

OPA691, see Figure 4.

Typically, channel switching is performed either on sync or

retrace time in the video signal. The two inputs are approxi-

mately equal at this time. The “make-before-break” disable

characteristic of the OPA691 ensures that there is always

one amplifier controlling the line when using a wired-OR

circuit like that presented in Figure 4. Since both inputs may

be on for a short period during the transition between

channels, the outputs are combined through the output

impedance matching resistors (82.5Ω in this case). When

one channel is disabled, its feedback network forms part of

the output impedance and slightly attenuates the signal in

getting out onto the cable. The gain and output matching

resistor have been slightly increased to get a signal gain of

+1 at the matched load and provide a 75Ω output impedance

to the cable. The video multiplexer connection (see Figure 4)

WIDEBAND INVERTING SUMMING AMPLIFIER

Since the signal bandwidth for a current feedback op amp may

be controlled independently of the noise gain (NG, which is

normally the same as the noninverting signal gain), very

broadband inverting summing stages may be implemented

using the OPA691. The circuit on the front page of this data

sheet shows an example inverting summing amplifier where

the resistor values have been adjusted to maintain both

maximum bandwidth and input impedance matching. If each

RF signal is assumed to be driven from a 50Ω source, the NG

for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The total

feedback impedance (from V_Oto the inverting error current) is

+5V

R_F

+5V

360Ω

R_G

120Ω

Clock

ADS823

10-Bit

60MSPS

0.1µF

50Ω

Input

OPA691

2Vp-p

22pF

0.5Vp-p

0.1µF

CM

DIS

2kΩ

+3.5V

REFT

0.1µF

+2.5V DC Bias

+1.5V

REFB

0.1µF

FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver.

OPA691

12

SBOS226A

www.ti.com

also ensures that the maximum differential voltage across

the inputs of the unselected channel do not exceed the rated

±1.2V maximum for standard video signal levels.

control of one amplifier or the other due to the “make-before-

break” disable timing. In this case, the switching glitches for

two 0V inputs drop to < 20mV.

The section on Disable Operation shows the turn-on and

turn-off switching glitches using a grounded input for a single

channel is typically less than ±50mV. Where two outputs are

switched (see Figure 6), the output line is always under the

4-CHANNEL FREQUENCY CHANNELIZER

The circuit of Figure 5 is a 4-channel multiplexer. In this

circuit the OPA691 provides the drive for all 4 channels.

+5V

2kΩ

V_DIS

+5V

Video 1

DIS

OPA691

75Ω

82.5Ω

–5V

340Ω

402Ω

75Ω Cable

RG-59

+5V

82.5Ω

OPA691

Video 2

DIS

75Ω

2kΩ

–5V

FIGURE 4. 2-Channel Video Multiplexer.

+5V

DIS 1

75Ω

59Ω

#1

OPA691

75Ω

R_O

–5V

402Ω

+5V

DIS 2

DIS 3

DIS 4

75Ω

59Ω

#2

OPA691

75Ω

R_O

+5V

–5V

402Ω

75Ω Cable

V_OUT

OPA691

RG-59

402Ω

+5V

75Ω Load

75Ω

–5V

59Ω

#3

OPA691

75Ω

R_O

–5V

402Ω

+5V

75Ω

59Ω

#4

OPA691

75Ω

R_O

–5V

402Ω

FIGURE 5. 4-Channel Frequency Channelizer.

OPA691

SBOS226A

13

www.ti.com

Each channel includes a bandpass filter. Each bandpass

filter is set for a different frequency band. This allows the

channelizing part of this circuit. The role of the channelizers

OPA691s is to provide impedance isolation. This is done

through the use of four matching resistances (59Ω in this

case). These matching resistors ensure that the signals will

combine during the transition between channels. They have

been used to get a gain of +1 at the load.

Bringing the signal in through a step-up transformer to the

inverting input gain resistor has several advantages for the

OPA691. First, the decoupling capacitor on the noninverting

input eliminates the contribution of the noninverting input current

noise to the output noise. Secondly, the noninverting input noise

voltage of the op amp is actually attenuated if reflected to the

input side of R_G. Using the 1:2 (turns ratio) step-up transformer

reflects the 50Ω source impedance at the primary through to the

secondary as a 200Ω source impedance (and the 200Ω R_G

resistor is reflected through to the transformer primary as a 50Ω

input matching impedance). The noise gain to the amplifier

output is then 1 + 600/400 = 2.5V/V. Taking the op amp’s

2.2nV/√Hz input voltage noise times this noise gain to the

output, then reflecting this noise term to the input side of the R_G

resistor, divides it by 3. This gives a net gain of 0.833 for the

noninverting input voltage noise when reflected to the input

point for the op amp circuit. This is further reduced when

referred back to the transformer primary.

This circuit may be used with a different number of channels.

Its limitation comes from the drive requirement for each

channel as well as the minimum acceptable return loss.

The output resistor value (R_O) to keep a gain of +1 at the load

depends on the number of channels. For the OPA691 with a

gain of 2 using R_F= 402Ω and R_G= 402Ω, Equation 1 is:

(1)

75Ω • n – 1 + 804Ω

(

)

[

]

•

241200Ω

The relatively low-gain IF amplifier circuit of Figure 6 gives a

12dB noise figure at the input of the transformer. Increasing

the R_Fresistor to 600Ω (once R_Gis set to 200Ω for input

impedance matching) will slightly reduce the bandwidth.

Measured results show 150MHz small-signal bandwidth for

the circuit of Figure 6 with exceptional flatness through

30MHz. Although the OPA691 does not show an intercept

characteristic for the 2-tone, 3rd-order intermodulation distor-

tion, it does hold a very high Spurious-Free Dynamic Range

(SFDR) through high output powers and frequencies. The

maximum single-tone power at the matched load for the

single-supply circuit of Figure 6 is 1dBm (this requires a

2.8Vp-p swing at the output pin of the OPA691 for the 2-tone

envelope). Measured 2-tone SFDR at this maximum load

power for the circuit of Figure 6 exceeds 55dBc for frequen-

cies to 20MHz.

R_O

=

1+

– 1

2

75Ω • n – 1 + 804Ω

(

)

[

]

SINGLE-SUPPLY “IF” AMPLIFIER

The high bandwidth provided by the OPA691 while operating

on a single +5V supply lends itself well to IF amplifier

applications. One of the advantages of using an op amp like

the OPA691 as an IF amplifier is that precise signal gain is

achieved along with much lower 3rd-order intermodulation

versus quiescent power dissipation. In addition, the OPA691

in the SOT23-6 package offers a very small package with a

power shutdown feature for portable applications. One con-

cern with using op amps for an IF amplifier is their relatively

high noise figures. It is sometimes suggested that an opti-

mum source resistance can be used to minimize op amp

noise figures. Adding a resistor to reach this optimum value

may improve the noise figure, but will actually decrease the

signal-to-noise ratio. A more effective way to move towards

an optimum source impedance is to bring the signal in

through an input transformer. Figure 6 shows an example

that is particularly useful for the OPA691.

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Several PC boards are available to assist in the initial

evaluation of circuit performance using the OPA691 in its two

package styles. All of these are available free as an

unpopulated PC board delivered with descriptive documen-

tation. The summary information for these boards is shown

in the table below.

+5V

Power-supply

decoupling not shown.

5kΩ

DIS

BOARD

PART

NUMBER

LITERATURE

REQUEST

NUMBER

50Ω

1µF

5kΩ

PRODUCT

PACKAGE

V_O

OPA691

OPA691ID

OPA691IDBV

SO-8

SOT23-6

DEM-OPA68xU

DEM-OPA6xxN

SBOU009

SBOU010

50Ω Load

50Ω Source

R_G

200Ω

R_F

600Ω

1:2

To request any of these boards, check the Texas Instru-

ments web site at www.ti.com.

V_I

V_O

V_I

= 3V/V (9.54dB)

MACROMODELS AND APPLICATIONS SUPPORT

0.1µF

Computer simulation of circuit performance using SPICE is

often useful when analyzing the performance of analog

circuits and systems. This is particularly true for video and RF

FIGURE 6. Low-Noise, Single-Supply IF Amplifier.

14

OPA691

SBOS226A

www.ti.com

R_I, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA691 is typically about 35Ω.

amplifier circuits where parasitic capacitance and inductance

can have a major effect on circuit performance. A SPICE

model for the OPA691 is available through the TI web site

(www.ti.com). These models do a good job of predicting

small-signal AC and transient performance under a wide

variety of operating conditions. They do not do as well in

predicting the harmonic distortion or dG/dφ characteristics.

These models do not attempt to distinguish between the

package types in their small-signal AC performance.

A current feedback op amp senses an error current in the

inverting node (as opposed to a differential input error volt-

age for a voltage feedback op amp) and passes this on to the

output through an internal frequency dependent transimped-

ance gain. The Typical Characteristics show this open-loop

transimpedance response. This is analogous to the open-

loop voltage gain curve for a voltage feedback op amp.

Developing the transfer function for the circuit of Figure 7

gives Equation 1:

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO

OPTIMIZE BANDWIDTH

R_F

α 1+

R_G

R_F+ R_I1+

Z_(S)

V_O

αNG

R_F+ R_ING

(2)

=

A current feedback op amp like the OPA691 can hold an

almost constant bandwidth over signal gain settings with the

proper adjustment of the external resistor values. This is

shown in the Typical Characteristic curves; the small-signal

bandwidth decreases only slightly with increasing gain. Those

curves also show that the feedback resistor has been changed

for each gain setting. The resistor “values” on the inverting

side of the circuit for a current feedback op amp can be

treated as frequency response compensation elements while

their “ratios” set the signal gain. Figure 7 shows the small-

signal frequency response analysis circuit for the OPA691.

V

R_F

I

1+

Z_S

R_G

1+

R_F

NG = 1+

R_G

This is written in a loop-gain analysis format where the errors

arising from a non-infinite open-loop gain are shown in the

denominator. If Z_(S)were infinite over all frequencies, the

denominator of Equation 1 would reduce to 1 and the ideal

desired signal gain shown in the numerator would be achieved.

The fraction in the denominator of Equation 1 determines the

frequency response. Equation 2 shows this as the loop-gain

equation:

V_I

Z_(S)

= Loop Gain

(3)

R_F+ R_ING

α

V_O

If 20 • log (R_F+ NG • R_I) were drawn on top of the open-loop

transimpedance plot, the difference between the two would

be the loop gain at a given frequency. Eventually, Z_(S)rolls off

to equal the denominator of Equation 2 at which point the

loop gain has reduced to 1 (and the curves have intersected).

This point of equality is where the amplifier’s closed-loop

frequency response given by Equation 1 will start to roll off,

and is exactly analogous to the frequency at which the noise

gain equals the open-loop voltage gain for a voltage feed-

back op amp. The difference here is that the total impedance

in the denominator of Equation 2 may be controlled some-

what separately from the desired signal gain (or NG).

R_I

Z_(S)i_ERR

i_ERR

R_F

R_G

FIGURE 7. Recommended Feedback Resistor versus Noise Gain.

The key elements of this current feedback op amp model are:

The OPA691 is internally compensated to give a maxi-

mally flat frequency response for R_F= 402Ω at NG = 2 on

±5V supplies. Evaluating the denominator of Equation 2

(which is the feedback transimpedance) gives an optimal

target of 472Ω. As the signal gain changes, the contribu-

tion of the NG • R_Iterm in the feedback transimpedance

will change, but the total can be held constant by adjust-

ing R_F. Equation 4 gives an approximate equation for

optimum R_Fover signal gain:

α → Buffer gain from the noninverting input to the inverting input

R_I→ Buffer output impedance

i

_ERR→ Feedback error current signal

Z(s) →Frequency dependent open-loop transimpedance gain from i_ERRto V_O

The buffer gain is typically very close to 1.00 and is normally

neglected from signal gain considerations. It will, however,

set the CMRR for a single op amp differential ampli-

fier configuration. For a buffer gain α < 1.0, the CMRR =

–20 • log (1– α) dB.

(4)

R_F= 472Ω – NG R_I

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As the desired signal gain increases, this equation will

eventually predict a negative R_F. A somewhat subjective limit

to this adjustment can also be set by holding R_Gto a

minimum value of 20Ω. Lower values will load both the buffer

stage at the input and the output stage if R_Fgets too low—

actually decreasing the bandwidth. Figure 8 shows the rec-

ommended R_Fversus NG for both ±5V and a single +5V

operation. The values for R_Fversus gain shown here are

approximately equal to the values used to generate the

Typical Characteristics. They differ in that the optimized

values used in the Typical Characteristics are also correcting

for board parasitics not considered in the simplified analysis

leading to Equation 3. The values shown in Figure 8 give a

good starting point for design where bandwidth optimization

is desired.

(e.g., integrators, transimpedance, and some filters) should

consider the unity-gain stable voltage feedback OPA680,

since the feedback resistor is the compensation element for a

current feedback op amp. Wideband inverting operation (and

especially summing) is particularly suited to the OPA691. See

Figure 9 for a typical inverting configuration where the I/O

impedances and signal gain from Figure 1 are retained in an

inverting circuit configuration.

+5V

Power-supply

decoupling

not shown.

50Ω Load

DIS

V_O

50Ω

OPA691

50Ω

Source

600

500

R_G

188Ω

R_F

374Ω

V_I

+5V

R_M

400

68.1Ω

–5V

300

200

±5V

100

FIGURE 9. Inverting Gain of –2 with Impedance Matching.

In the inverting configuration, two key design considerations

must be noted. The first is that the gain resistor (R_G)

becomes part of the signal channel input impedance. If input

impedance matching is desired (which is beneficial when-

ever the signal is coupled through a cable, twisted-pair, long

PC board trace, or other transmission line conductor), it is

normally necessary to add an additional matching resistor to

ground. R_Gby itself is normally not set to the required input

impedance since its value, along with the desired gain, will

determine an R_Fwhich may be non-optimal from a frequency

response standpoint. The total input impedance for the

source becomes the parallel combination of R_Gand R_M.

0

5

10

15

20

Noise Gain

FIGURE 8. Feedback Resistor vs Noise Gain.

The total impedance going into the inverting input may be

used to adjust the closed-loop signal bandwidth. Inserting a

series resistor between the inverting input and the summing

junction will increase the feedback impedance (denominator

of Equation 2), decreasing the bandwidth. This approach to

bandwidth control is used for the inverting summing circuit on

the front page. The internal buffer output impedance for the

OPA691 is slightly influenced by the source impedance

looking out of the noninverting input terminal. High source

resistors will have the effect of increasing R_I, decreasing the

bandwidth. For those single-supply applications which de-

velop a midpoint bias at the noninverting input through high

valued resistors, the decoupling capacitor is essential for

power-supply noise rejection, noninverting input noise cur-

rent shunting, and to minimize the high frequency value for

R_Iin Figure 7.

The second major consideration, touched on in the previous

paragraph, is that the signal source impedance becomes

part of the noise gain equation and will have slight effect on

the bandwidth through Equation 1. The values shown in

Figure 9 have accounted for this by slightly decreasing R_F

(from Figure 1) to re-optimize the bandwidth for the noise

gain of Figure 9 (NG = 2.73) In the example of Figure 9, the

R_Mvalue combines in parallel with the external 50Ω source

impedance, yielding an effective driving impedance of

50Ω || 68Ω = 28.8Ω. This impedance is added in series with

R_Gfor calculating the noise gain—which gives NG = 2.73.

This value, along with the R_Fof Figure 9 and the inverting

input impedance of 35Ω, are inserted into Equation 3 to get

a feedback transimpedance nearly equal to the 472Ω opti-

mum value.

INVERTING AMPLIFIER OPERATION

Since the OPA691 is a general-purpose, wideband current

feedback op amp, most of the familiar op amp application

circuits are available to the designer. Those applications that

require considerable flexibility in the feedback element

Note that the noninverting input in this bipolar supply invert-

ing application is connected directly to ground. It is often

suggested that an additional resistor be connected to ground

OPA691

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on the noninverting input to achieve bias current error can-

cellation at the output. The input bias currents for a current

feedback op amp are not generally matched in either magni-

tude or polarity. Connecting a resistor to ground on the

noninverting input of the OPA691 in the circuit of Figure 9 will

actually provide additional gain for that input’s bias and noise

currents, but will not decrease the output DC error since the

input bias currents are not matched.

prove ADC linearity. A high-speed, high open-loop gain

amplifier like the OPA691 can be very susceptible to de-

creased stability and closed-loop response peaking when a

capacitive load is placed directly on the output pin. When the

amplifier’s open-loop output resistance is considered, this

capacitive load introduces an additional pole in the signal

path that can decrease the phase margin. Several external

solutions to this problem have been suggested. When the

primary considerations are frequency response flatness, pulse

response fidelity, and/or distortion, the simplest and most

effective solution is to isolate the capacitive load from the

feedback loop by inserting a series isolation resistor between

the amplifier output and the capacitive load. This does not

eliminate the pole from the loop response, but rather shifts it

and adds a zero at a higher frequency. The additional zero

acts to cancel the phase lag from the capacitive load pole,

thus increasing the phase margin and improving stability.

OUTPUT CURRENT AND VOLTAGE

The OPA691 provides output voltage and current capabilities

that are unsurpassed in a low-cost monolithic op amp. Under

no-load conditions at 25°C, the output voltage typically swings

closer than 1V to either supply rail; the +25°C swing limit is

within 1.2V of either rail. Into a 15Ω load (the minimum tested

load), it is tested to deliver more than ±160mA.

The specifications described above, though familiar in the

industry, consider voltage and current limits separately. In

many applications, it is the voltage • current, or V-I product,

which is more relevant to circuit operation. Refer to the

“Output Voltage and Current Limitations” plot in the Typical

Characteristics. The X- and Y-axes of this graph show the

zero-voltage output current limit and the zero-current output

voltage limit, respectively. The four quadrants give a more

detailed view of the OPA691’s output drive capabilities,

noting that the graph is bounded by a “Safe Operating Area”

of 1W maximum internal power dissipation. Superimposing

resistor load lines onto the plot shows that the OPA691 can

drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the

output capabilities or the 1W dissipation limit. A 100Ω load

line (the standard test circuit load) shows the full ±3.9V

output swing capability, as shown in the Typical Specifica-

tions.

The Typical Characteristics show the recommended R_Sver-

sus Capacitive Load and the resulting frequency response at

the load. Parasitic capacitive loads greater than 2pF can

begin to degrade the performance of the OPA691. Long PC

board traces, unmatched cables, and connections to multiple

devices can easily cause this value to be exceeded. Always

consider this effect carefully, and add the recommended

series resistor as close as possible to the OPA691 output pin

(see Board Layout Guidelines).

DISTORTION PERFORMANCE

The OPA691 provides good distortion performance into a

100Ω load on ±5V supplies. Relative to alternative solutions,

it provides exceptional performance into lighter loads and/or

operating on a single +5V supply. Generally, until the funda-

mental signal reaches very high frequency or power levels,

the 2nd-harmonic will dominate the distortion with a negli-

gible 3rd-harmonic component. Focusing then on the 2nd-

harmonic, increasing the load impedance improves distortion

directly. Remember that the total load includes the feedback

network—in the noninverting configuration (see Figure 1) this

is the sum of R_F+ R_G, while in the inverting configuration it

is just R_F. Also, providing an additional supply decoupling

capacitor (0.1µF) between the supply pins (for bipolar opera-

tion) improves the 2nd-order distortion slightly (3dB to 6dB).

The minimum specified output voltage and current over-

temperature are set by worst-case simulations at the cold

temperature extreme. Only at cold startup will the output

current and voltage decrease to the numbers shown in the

Electrical Characteristic tables. As the output transistors

deliver power, their junction temperatures will increase, de-

creasing their V_BE’s (increasing the available output voltage

swing) and increasing their current gains (increasing the

available output current). In steady-state operation, the avail-

able output voltage and current will always be greater than

that shown in the over-temperature specifications since the

output stage junction temperatures will be higher than the

minimum specified operating ambient.

In most op amps, increasing the output voltage swing in-

creases harmonic distortion directly. The Typical Character-

istics show the 2nd-harmonic increasing at a little less than

the expected 2x rate while the 3rd-harmonic increases at a

little less than the expected 3x rate. Where the test power

doubles, the 2nd-harmonic increases by less than the ex-

pected 6dB while the 3rd-harmonic increases by less than

the expected 12dB. This also shows up in the 2-tone,

3rd-order intermodulation spurious (IM3) response curves.

The 3rd-order spurious levels are extremely low at low output

power levels. The output stage continues to hold them low

even as the fundamental power reaches very high levels. As

the Typical Characteristics show, the spurious intermodulation

powers do not increase as predicted by a traditional intercept

model. As the fundamental power level increases, the

To protect the output stage from accidental shorts to ground

and the power supplies, output short-circuit protection is

included in the OPA691. The circuit acts to limit the maximum

source or sink current to approximately 250mA.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an ADC—including additional

external capacitance which may be recommended to im-

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dynamic range does not decrease significantly. For two

tones centered at 20MHz, with 10dBm/tone into a matched

50Ω load (i.e., 2Vp-p for each tone at the load, which requires

8Vp-p for the overall 2-tone envelope at the output pin), the

Typical Characteristics show 48dBc difference between the

test-tone power and the 3rd-order intermodulation spurious

levels. This exceptional performance improves further when

operating at lower frequencies.

Dividing this expression by the noise gain (NG = (1 + R_F/R_G))

will give the equivalent input-referred spot noise voltage at

the noninverting input, as shown in Equation 6.

(6)

2

I_BIR_F

NG

4kTR_F

NG

2

E_N

=

E_NI+ I_BNR_S+ 4kTR_S

+

(

)

Evaluating these two equations for the OPA691 circuit and

component values (see Figure 1) will give a total output spot

noise voltage of 8.0nV/√Hz and a total equivalent input spot

noise voltage of 4.0nV/√Hz. This total input-referred spot

noise voltage is higher than the 1.7nV/√Hz specification for

the op amp voltage noise alone. This reflects the noise

added to the output by the inverting current noise times the

feedback resistor. If the feedback resistor is reduced in high

gain configurations (as suggested previously), the total input-

referred voltage noise given by Equation 5 will approach just

the 1.7nV/√Hz of the op amp itself. For example, going to a

gain of +10 using R_F= 180Ω will give a total input-referred

NOISE PERFORMANCE

Wideband current feedback op amps generally have a higher

output noise than comparable voltage feedback op amps. The

OPA691 offers an excellent balance between voltage and

current noise terms to achieve low output noise. The inverting

current noise (15pA/√Hz) is significantly lower than earlier

solutions while the input voltage noise (1.7nV/√Hz) is lower

than most unity-gain stable, wideband, voltage feedback op

amps. This low input voltage noise was achieved at the price

of higher noninverting input current noise (12pA/√Hz). As long

as the AC source impedance looking out of the noninverting

node is less than 100Ω, this current noise will not contribute

significantly to the total output noise. The op amp input voltage

noise and the two input current noise terms combine to give

low output noise under a wide variety of operating conditions.

Figure 10 shows the op amp noise analysis model with all the

noise terms included. In this model, all noise terms are taken

to be noise voltage or current density terms in either nV/√Hz

noise of 2.1nV/√Hz

.

DC ACCURACY AND OFFSET CONTROL

A current feedback op amp like the OPA691 provides excep-

tional bandwidth in high gains, giving fast pulse settling but

only moderate DC accuracy. The Typical Specifications show

an input offset voltage comparable to high-speed voltage

feedback amplifiers. However, the two input bias currents are

somewhat higher and are unmatched. Whereas bias current

cancellation techniques are very effective with most voltage

feedback op amps, they do not generally reduce the output DC

offset for wideband current feedback op amps. Since the two

input bias currents are unrelated in both magnitude and

polarity, matching the source impedance looking out of each

input to reduce their error contribution to the output is ineffec-

tive. Evaluating the configuration of Figure 1, using worst-case

+25°C input offset voltage and the two input bias currents,

gives a worst-case output offset range equal to:

or pA/√Hz

.

E_NI

E_O

OPA691

R_S

I_BN

E_RS

R_F

√4kTR_S

± (NG • V_OS(MAX)) + (I_BN• R_S/2 • NG) ± (I_BI• R_F)

where NG = noninverting signal gain

= ± (2 • 2.5mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA)

= ±5mV + 1.75mV ± 10.05mV

√4kTR_F

I_BI

R_G

4kT

R_G

4kT = 1.6E –20J

at 290°K

= –13.3mV → +16.8mV

A fine-scale, output offset null, or DC operating point adjust-

ment, is sometimes required. Numerous techniques are

available for introducing DC offset control into an op amp

circuit. Most simple adjustment techniques do not correct for

temperature drift. It is possible to combine a lower speed,

precision op amp with the OPA691 to get the DC accuracy

of the precision op amp along with the signal bandwidth of

the OPA691. See Figure 11 for a noninverting G = +10 circuit

that holds an output offset voltage less than ±7.5mV over-

temperature with > 150MHz signal bandwidth.

FIGURE 10. Op Amp Noise Analysis Model.

The total output spot noise voltage can be computed as the

square root of the sum of all squared output noise voltage

contributors. Equation 5 shows the general form for the

output noise voltage using the terms shown in Figure 10.

(5)

2

E_NI+ I_BNR_S+ 4kTR_SNG²+ I R

+ 4kTR_FNG

2

This DC-coupled circuit provides very high signal bandwidth

using the OPA691. At lower frequencies, the output voltage

is attenuated by the signal gain and compared to the original

E_O

=

(

)

(

)

BI

F

OPA691

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input voltage at the inputs of the OPA237 (this is a low-cost,

precision voltage feedback op amp with 1.5MHz gain band-

width product). If these two don’t agree (due to DC offsets

introduced by the OPA691), the OPA237 sums in a correc-

tion current through the 2.86kΩ inverting summing path.

Several design considerations will allow this circuit to be

optimized. First, the feedback to the OPA237’s noninverting

input must be precisely matched to the high-speed signal

gain. Making the 2kΩ resistor to ground an adjustable resis-

tor would allow the low and high frequency gains to

be precisely matched. Secondly, the crossover frequency

region where the OPA237 passes control to the OPA691

must occur with exceptional phase linearity. These two

issues reduce to designing for pole/zero cancellation in the

overall transfer function. Using the 2.86kΩ resistor will nomi-

nally satisfy this requirement for the circuit in Figure 11.

Perfect cancellation over process and temperature is not

possible. This initial resistor setting and precise gain match-

ing, however, will minimize long-term pulse settling tails.

+V_S

15kΩ

Q1

25kΩ

110kΩ

I_S

V_DIS

Control

–V_S

FIGURE 12. Simplified Disable Control Circuit.

When disabled, the output and input nodes go to a high

impedance state. If the OPA691 is operating in a gain of +1,

this will show a very high impedance (4pF || 1MΩ) at the

output and exceptional signal isolation. If operating at a

gain greater than +1, the total feedback network resistance

(R_F+ R_G) will appear as the impedance looking back into the

output, but the circuit will still show very high forward and

reverse isolation. If configured as an inverting amplifier, the

input and output will be connected through the feedback

network resistance (R_F+ R_G) giving relatively poor input-to-

output isolation.

+5V

Power supply

de-coupling not shown

DIS

V_I

V_O

OPA691

+5V

1.8kΩ

180Ω

2.86kΩ

–5V

20Ω

OPA237

One key parameter in disable operation is the output glitch

when switching in and out of the disabled mode. Figure 13

shows these glitches for the circuit of Figure 1 with the input

signal set to 0V. The glitch waveform at the output pin is

plotted along with the DIS pin voltage.

–5V

18kΩ

The transition edge rate (dV/dT) of the DIS control line will

influence this glitch. For the plot of Figure 12, the edge rate

was reduced until no further reduction in glitch amplitude was

observed. This approximately 1V/ns maximum slew rate may

be achieved by adding a simple RC filter into the V_DISpin

from a higher speed logic line. If extremely fast transition

logic is used, a 2kΩ series resistor between the logic gate

and the DIS input pin will provide adequate bandlimiting

using just the parasitic input capacitance on the DIS pin

while still ensuring an adequate logic level swing.

2kΩ

FIGURE 11. Wideband, DC Connected Composite Circuit.

DISABLE OPERATION

The OPA691 provides an optional disable feature that may

be used to reduce system power. If the DIS control pin is left

unconnected, the OPA691 will operate normally. To disable,

the control pin must be asserted LOW. Figure 12 shows a

simplified internal circuit for the disable control feature.

6.0

4.0

In normal operation, base current to Q1 is provided through

the 110kΩ resistor while the emitter current through the 15kΩ

resistor sets up a voltage drop that is inadequate to turn on

the two diodes in Q1’s emitter. As V_DISis pulled LOW,

additional current is pulled through the 15kΩ resistor eventu-

ally turning on these two diodes (≈ 75µA). At this point, any

further current pulled out of V_DISgoes through those diodes

holding the emitter-base voltage of Q1 at approximately 0V.

This shuts off the collector current out of Q1, turning the

amplifier off. The supply current in the disable mode are only

those required to operate the circuit of Figure 12. Additional

circuitry ensures that turn-on time occurs faster than turn-off

time (make-before-break).

2.0

0

V_DIS

30

20

Output Voltage

(0V Input)

10

0

–10

–20

–30

Time (20ns/div)

FIGURE 13. Disable/Enable Glitch.

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THERMAL ANALYSIS

b) Minimize the distance (< 0.25") from the power-supply

pins to high-frequency 0.1µF decoupling capacitors. At the

device pins, the ground and power plane layout should not

be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. The power-supply

connections (on pins 4 and 7) should always be decoupled

with these capacitors. An optional supply decoupling capaci-

tor across the two power supplies (for bipolar operation) will

improve 2nd-harmonic distortion performance. Larger (2.2µF

to 6.8µF) decoupling capacitors, effective at lower frequen-

cies, should also be used on the main supply pins. These

may be placed somewhat farther from the device and may be

shared among several devices in the same area of the PC

board.

Due to the high output power capability of the OPA691,

heatsinking or forced airflow may be required under extreme

operating conditions. Maximum desired junction temperature

will set the maximum allowed internal power dissipation, as

described below. In no case should the maximum junction

temperature be allowed to exceed 175°C.

Operating junction temperature (T_J) is given by T_A+ P_D• θ_JA

.

The total internal power dissipation (P_D) is the sum of

quiescent power (P_DQ) and additional power dissipated in the

output stage (P_DL) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total

supply voltage across the part. P_DLwill depend on the

required output signal and load but would, for a grounded

resistive load, be at a maximum when the output is fixed at

a voltage equal to 1/2 either supply voltage (for equal bipolar

supplies). Under this condition P_DL= V_S²/(4 • R_L) where R_L

includes feedback network loading.

c) Careful selection and placement of external compo-

nents will preserve the high-frequency performance of

the OPA691. Resistors should be a very low reactance type.

Surface-mount resistors work best and allow a tighter overall

layout. Metal-film and carbon composition, axially-leaded

resistors can also provide good high-frequency performance.

Again, keep their leads and PC board trace length as short

as possible. Never use wirewound type resistors in a high-

frequency application. Since the output pin and inverting

input pin are the most sensitive to parasitic capacitance,

always position the feedback and series output resistor, if

any, as close as possible to the output pin. Other network

components, such as noninverting input termination resis-

tors, should also be placed close to the package. Where

double-side component mounting is allowed, place the feed-

back resistor directly under the package on the other side of

the board between the output and inverting input pins. The

frequency response is primarily determined by the feedback

resistor value as described previously. Increasing its value

will reduce the bandwidth, while decreasing it will give a more

peaked frequency response. The 402Ω feedback resistor

used in the Electrical Characteristic tables at a gain of +2 on

±5V supplies is a good starting point for design. Note that a

453Ω feedback resistor, rather than a direct short, is recom-

mended for the unity-gain follower application. A current

feedback op amp requires a feedback resistor even in the

unity-gain follower configuration to control stability.

Note that it is the power in the output stage and not in the

load that determines internal power dissipation.

As a worst-case example, compute the maximum T_Jusing an

OPA691IDBV (SOT23-6 package) in the circuit of Figure 1

operating at the maximum specified ambient temperature of

+85°C and driving a grounded 20Ω load to +2.5V DC:

P_D= 10V • 5.7mA + 5²/(4 • (20Ω || 804Ω)) = 377mΩ

Maximum T_J= +85°C + (0.377W • (150°C/W) = 141.5°C

Although this is still well below the specified maximum

junction temperature, system reliability considerations may

require lower junction temperatures. Remember, this is a

worst-case internal power dissipation—use your actual sig-

nal and load to computer P_DL. The highest possible internal

dissipation will occur if the load requires current to be forced

into the output for positive output voltages or sourced from

the output for negative output voltages. This puts a high

current through a large internal voltage drop in the output

transistors. The “Output Voltage and Current Limitations” plot

shown in the Typical Characteristics includes a boundary for

1W maximum internal power dissipation under these condi-

tions.

BOARD LAYOUT GUIDELINES

d) Connections to other wideband devices on the board

may be made with short, direct traces or through onboard

transmission lines. For short connections, consider the trace

and the input to the next device as a lumped capacitive load.

Relatively wide traces (50mils to 100mils) should be used,

preferably with ground and power planes opened up around

them. Estimate the total capacitive load and set R_Sfrom the

plot of recommended R_Sversus Capacitive Load. Low para-

sitic capacitive loads (< 5pF) may not need an R_Ssince the

OPA691 is nominally compensated to operate with a 2pF

parasitic load. If a long trace is required, and the 6dB signal

loss intrinsic to a doubly-terminated transmission line is

acceptable, implement a matched impedance transmission

line using microstrip or stripline techniques (consult an ECL

Achieving optimum performance with a high-frequency am-

plifier like the OPA691 requires careful attention to board

layout parasitics and external component types. Recommen-

dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Parasitic capacitance on the output and

inverting input pins can cause instability: on the noninverting

input, it can react with the source impedance to cause

unintentional bandlimiting. To reduce unwanted capacitance,

a window around the signal I/O pins should be opened in all

of the ground and power planes around those pins. Other-

wise, ground and power planes should be unbroken else-

where on the board.

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20

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design handbook for microstrip and stripline layout tech-

niques). A 50Ω environment is normally not necessary on

board, and in fact, a higher impedance environment will

improve distortion, as shown in the Distortion versus Load

plots. With a characteristic board trace impedance defined

based on board material and trace dimensions, a matching

series resistor into the trace from the output of the OPA691

is used as well as a terminating shunt resistor at the input of

the destination device. Remember also that the terminating

impedance will be the parallel combination of the shunt

resistor and the input impedance of the destination device:

this total effective impedance should be set to match the

trace impedance. The high output voltage and current capa-

bility of the OPA691 allows multiple destination devices to be

handled as separate transmission lines, each with their own

series and shunt terminations. If the 6dB attenuation of a

doubly-terminated transmission line is unacceptable, a long

trace can be series-terminated at the source end only. Treat

the trace as a capacitive load in this case and set the series

resistor value as shown in the plot of R_Sversus Capacitive

Load. This will not preserve signal integrity as well as a

doubly-terminated line. If the input impedance of the destina-

tion device is low, there will be some signal attenuation due

to the voltage divider formed by the series output into the

terminating impedance.

INPUT AND ESD PROTECTION

The OPA691 is built using a very high speed complementary

bipolar process. The internal junction breakdown voltages

are relatively low for these very small geometry devices.

These breakdowns are reflected in the Absolute Maximum

Ratings table. All device pins have limited ESD protection

using internal diodes to the power supplies, as shown in

Figure 14.

These diodes provide moderate protection to input overdrive

voltages above the supplies as well. The protection diodes

can typically support 30mA continuous current. Where higher

currents are possible (e.g., in systems with ±15V supply parts

driving into the OPA691), current-limiting series resistors

should be added into the two inputs. Keep these resistor

values as low as possible since high values degrade both

noise performance and frequency response.

+V_CC

External

Internal

Circuitry

–V_CC

e) Socketing a high-speed part like the OPA691 is not

recommended. The additional lead length and pin-to-pin

capacitance introduced by the socket can create an ex-

tremely troublesome parasitic network which can make it

almost impossible to achieve a smooth, stable frequency

response. Best results are obtained by soldering the OPA691

onto the board.

FIGURE 14. Internal ESD Protection.

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PACKAGE DRAWINGS

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.020 (0,51)

0.014 (0,35)

0.050 (1,27)

8

0.010 (0,25)

5

0.244 (6,20)

0.228 (5,80)

0.008 (0,20) NOM

0.157 (4,00)

0.150 (3,81)

Gage Plane

1

4

0.010 (0,25)

0°– 8°

A

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

0.069 (1,75) MAX

0.004 (0,10)

PINS **

8

14

16

DIM

A MAX

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/E 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

OPA691

22

SBOS226A

www.ti.com

PACKAGE DRAWINGS (Cont.)

DBV (R-PDSO-G6)

PLASTIC SMALL-OUTLINE

0,50

0,25

M

0,20

0,95

6X

6

4

0,15 NOM

1,70

1,50

3,00

2,60

1

3

Gage Plane

3,00

2,80

0,25

0 –8

0,55

0,35

Seating Plane

0,10

1,45

0,95

0,05 MIN

4073253-5/G 01/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation.

OPA691

SBOS226A

23

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

9-Dec-2004

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

OPA691ID

OPA691IDBVR

OPA691IDBVT

OPA691IDR

ACTIVE

SOIC

D

8

6

8

100

3000

250

None

CU SNPB

Level-3-235C-168 HR

SOT-23

SOIC

DBV

D

CU NIPDAU Level-3-220C-168 HR

2500

CU SNPB

Level-3-235C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	OPA691ID
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	1 week
风险等级：	0.76
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	181641
Samacsys Pin Count：	8
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	D (R-PDSO-G8)
Samacsys Released Date：	2015-04-13 16:55:55
Is Samacsys：	N
放大器类型：	OPERATIONAL AMPLIFIER
架构：	CURRENT-FEEDBACK
最大平均偏置电流 (IIB)：	35 µA
25C 时的最大偏置电流 (IIB)：	40 µA
最小共模抑制比：	52 dB
标称共模抑制比：	56 dB
频率补偿：	YES
最大输入失调电压：	2500 µV
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
低-偏置：	NO
低-失调：	NO
微功率：	NO
湿度敏感等级：	2
负供电电压上限：	-6.5 V
标称负供电电压 (Vsup)：	-5 V
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TUBE
峰值回流温度（摄氏度）：	260
功率：	NO
电源：	5/+-5 V
可编程功率：	NO
认证状态：	Not Qualified
座面最大高度：	1.75 mm
最小摆率：	550 V/us
标称压摆率：	2100 V/us
子类别：	Operational Amplifier
最大压摆率：	5.3 mA
供电电压上限：	6.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	BIPOLAR
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
标称均一增益带宽：	280000 kHz
宽带：	YES
宽度：	3.91 mm
Base Number Matches：	1

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