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PGA2505

Burr-Brown Audio

www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009

™ Digitally-Controlled

MICROPHONE PREAMPLIFIER

1

FEATURES

APPLICATIONS

•

MICROPHONE PREAMPLIFIERS AND MIXERS

DIGITAL MIXERS AND RECORDERS

DIGITAL AUDIO EDITING SYSTEMS

BROADCAST EQUIPMENT

234

•

FULLY DIFFERENTIAL lNPUT-TO-OUTPUT

ARCHITECTURE

•

DIGITALLY-CONTROLLED GAIN USING SPI™:

–

Gain Range: 9dB through 60dB,

3dB per Step

INTERCOMS

–

Unity (0dB) Gain Setting via Serial Port

DESCRIPTION

•

DYNAMIC PERFORMANCE:

The PGA2505 is

a

digitally-controlled, analog

–

Equivalent Input Noise with Z_S= 150Ω

microphone preamplifier designed for use as a

front-end for high-performance audio analog-to-digital

converters (ADCs). The PGA2505 features include

low noise, wide dynamic range, and a differential

signal path. An on-chip dc servo loop is employed to

minimize dc offset, while a common-mode servo

function may be used to enhance common-mode

rejection.SoundPlus™

and Gain = 30dB: –123dBu

–

Total Harmonic Distortion plus Noise

(THD+N) with Gain = 30dB: 0.0006%

•

ZERO CROSSING DETECTION MINIMIZES

AUDIBLE ARTIFACTS WHEN GAIN

SWITCHING

INTEGRATED DC SERVO MINIMIZES

OUTPUT OFFSET VOLTAGE

The PGA2505 features a gain range of 9dB through

60dB (3dB/step), along with a unity gain setting. The

wide gain range allows the PGA2505 to be used with

a variety of microphones. Gain settings and internal

functions are programmed using a 16-bit control

word, which is loaded using a simple serial port

interface. A serial data output pin provides support for

daisy-chained connection of multiple PGA2505

devices. Four programmable digital outputs are

provided for controlling the external switching of input

pads, phantom power, and high-pass filters. The

PGA2505 requires both +5V and –5V power supplies

and is available in a small SSOP-24 package.

•

COMMON-MODE SERVO IMPROVES CMRR

FOUR-WIRE SERIAL CONTROL PORT

INTERFACE:

–

Simple Interface to Microprocessor

or DSP Serial Ports

–

Supports Daisy-Chaining of Multiple

PGA2505 Devices

•

OVER-RANGE OUTPUT PIN PROVIDES

CLIPPING INDICATION

FOUR GENERAL-PURPOSE

DIGITAL OUTPUT PINS

•

±5V POWER SUPPLIES

AVAILABLE IN AN SSOP-24 PACKAGE

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

SoundPlus is a trademark of Texas Instruments Incorporated.

SPI is a trademark of Motorola, Inc..

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PGA2505

SBOS396B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

PGA2505

–0.3 to +5.5

UNIT

V

Supply Voltage, AGND or DGND to VA+

Supply Voltage, AGND or DGND to VA–

Supply Voltage, AGND or DGND to VD–

Voltage Difference, VA– to VD–

Ground Difference, AGND to DGND

Analog Input Voltage

+0.3 to –5.5

V

+0.3 to –5.5

V

±0.3

V

±0.3

V

(VA–) –0.3 to (VA+) +0.3

(DGND) – 0.3 to (VA+) + 0.3

±10

V

Digital Input Voltage

V

Input Current of All Pins Except Supply

mA

See Electrical Characteristics,

Thermal Resistance parameter

Power Dissipation

Junction Temperature Range, T_J

Operating Free-Air Temperature Range, T_A

Storage Temperature Range, T_STG

Human Body Model (HBM)

–40 to +150

–40 to +85

–60 to +150

2000

°C

V

ESD Ratings

Charged Device Model (CDM)

Machine Model (MM)

1000

V

150

V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not supported.

ORDERING INFORMATION⁽¹⁾

PRODUCT

PACKAGE-LEAD

PACKAGE DESIGNATOR

PACKAGE MARKING

PGA2505

SSOP-24

DB

PGA2505I

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

2

Product Folder Link(s): PGA2505

PGA2505

www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009

ELECTRICAL CHARACTERISTICS

At T_A= +25°C, VA+ = +5V, VA– = –5V, VD– = –5V, and V_COMIN = 0V, unless otherwise noted.

PGA2505

PARAMETERS

DC CHARACTERISTICS

CONDITIONS

MIN

TYP

MAX

UNIT

Step Size

Gain = 9dB through 60dB

All gain settings

3

dB

Gain Error

±0.5

AC CHARACTERISTICS

f_IN= 1kHz, Gain = 0dB, V_OUT= 3.5V_RMS

f_IN= 1kHz, Gain = 30dB, V_OUT= 3.5V_RMS

–110

–105

–100

–95

dB

THD+N

ANALOG INPUT

Maximum Input Voltage

Input Resistance

Per Input Pin

Gain = 0dB

VA– +1.5

VA+ –2.0

V

4600

9200

Ω

Differential

ANALOG OUTPUT

Output Voltage Range

Output Offset Voltage

Input-Referred Offset

Output Resistive Loading

Load Capacitance Stability

Short Circuit Current

DIGITAL CHARACTERISTICS

High-Level Input Voltage

Low-Level Input Voltage

High-Level Output Voltage

Low-Level Output Voltage

Input Leakage Current

POWER SUPPLY

Operating Voltage

VA+

V_COMIN = 0V, R_L= 600Ω

DC servo on, any gain

DC servo off, gain = 30dB

VA– +0.9

600

VA+ –0.9

±1

V

±0.08

±1

mV

Ω

100

pF

mA

10-second duration

V_IH

V_IL

+2.0

–0.3

VA+

0.8

V

V_OH

V_OL

I_IN

I_O= 200µA

(VA+) – 1.0

V

I_O= –3.2mA

0.4

10

V

2

µA

+4.75

–4.75

+5

–5

+5.25

–5.25

V

VA–

VD–

Quiescent Current

IA+

VA+ = +5V

VA– = –5V

VD– = –5V

30

1

40

2

mA

IA–

ID–

TEMPERATURE RANGE

Operating Free-Air Temperature

Range

T_A

–40

÷85

°C

Thermal Resistance

θ_JA

θ_JC

High-K board

72

42

°C/W

SSOP-24

3

Product Folder Link(s): PGA2505

PGA2505

SBOS396B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com

SWITCHING CHARACTERISTICS

Over operating free-air temperature range (unless otherwise noted).

PGA2505

PARAMETER

TEST CONDITIONS

MIN

0

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_PH

Serial clock (SCLK) frequency

Serial clock (SCLK) pulse width low

Serial clock (SCLK) pulse width high

6.25

80

t_PL

ns

TIMING REQUIREMENTS

Over operating free-air temperature range (unless otherwise noted).

PGA2505

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

INPUT TIMING

t_SDS

SDI setup time

SDI hold time

20

90

35

ns

t_SDH

t_CSCR

t_CFCS

CS falling to SCLK rising

SCLK falling to CS rising

OUTPUT TIMING

t_CSO

t_CFDO

t_CSZ

CS low to SDO active

35

60

ns

SCLK falling to SDO data valid

CS high to SDO high impedance

100

SERIAL PORT TIMING DIAGRAM

CS

t_SDS

t_CSCR

t_CFCS

t_SDH

SCLK

SDI

MSB

SDO

MSB

t_CSZ

t_CSO

t_CFDO

4

Product Folder Link(s): PGA2505

PGA2505

www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009

PIN CONFIGURATION

DB PACKAGE

SSOP-24

(TOP VIEW)

AGND

GPO1

GPO2

GPO3

GPO4

OVR

1

2

24 V_IN

+

23 V_IN

-

3

22 V_COMIN

21 C_S11

20 C_S12

19 C_S21

18 C_S22

17 VA-

16 VA+

4

5

6

PGA2505

DGND

SDI

7

8

CS

9

SCLK

SDO

10

11

15 V_OUT

+

14 V_OUT

-

VD- 12

13 VA-

PIN ASSIGNMENTS

TERMINAL

PIN#

NAME

AGND

GPO1

GPO2

GPO3

GPO4

OVR

DESCRIPTION

1

Analog Ground

2

General-Purpose CMOS Logic Output

Over Range Output (Active High)

Digital Ground

3

4

5

6

DGND

SDI

7

8

Serial Data Input

CS

9

Chip Select Input (Active Low)

Serial Data Clock Input

SCLK

SDO

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Serial Data Output

VD–

–5V Digital Supply

VA–

–5V Analog Supply

V_OUT

VA+

VA–

C_S22

C_S21

C_S12

C_S11

–

+

Inverting Analog Output

Noninverting Analog Output

+5V Analog Supply

–5V Analog Supply

External DC Servo Capacitor #2, Terminal 2

External DC Servo Capacitor #2, Terminal 1

External DC Servo Capacitor #1, Terminal 2

External DC Servo Capacitor #1, Terminal 1

Common Mode Voltage Input, 0V to +2.5V

Inverting Analog Input

V_COMIN

V_IN

–

+

V_IN

Noninverting Analog Input

5

Product Folder Link(s): PGA2505

PGA2505

SBOS396B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS

At T_A= +25°C, VA+ = +5V, VA– = –5V, VD– = –5V, and V_COMIN = 0V, unless otherwise noted.

EQUIVALENT INPUT NOISE AS A FUNCTION OF GAIN

WITH Z_S= 0Ω

WITH Z_S= 150Ω

-110

-112

-114

-116

-118

-120

-122

-124

-126

-112

-114

-116

-118

-120

-122

-124

-126

9

12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60

9

12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60

Gain (dB)

Figure 1.

Figure 2.

THD+N vs GAIN

THD+N vs GAIN AND NOISE vs GAIN

0.01

-60

-70

V_OUT= 4.0V_RMS

Z_S= 40W

-80

THD+N

with Z_S= 40W

-90

0.001

V_OUT= 4.0V_RMS

-100

-110

-120

-130

Noise

with Z_S= 0W

Reference 0dB = 4.0V_RMS

0.0001

9

12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60

9

12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60

Gain (dB)

Figure 3.

Figure 4.

THD + N vs FREQUENCY

(Z_S= 40Ω, R_L= 600Ω, V_COMIN = 0V, BW = 22Hz to 22kHz)

0.1

V_OUT= 4.0V_RMSDifferential for Gains =

THD + N vs FREQUENCY

(Z_S= 40Ω, R_L= 600Ω, V_COMIN = +2.5V, BW = 22Hz to 22kHz)

0.1

V_OUT= 2.0V_RMSDifferential for Gains = 12dB,

12dB, 24dB, 30dB, 36dB, 48dB, and 60dB

V_OUT= 3.5V_RMSDifferential for Gain = 0dB

60dB

24dB, 30dB, 36dB, 48dB, and 60dB

60dB

V_OUT= 1V_RMSDifferential for Gain = 0dB

0.01

48dB

36dB

24dB

36dB

0dB

30dB

0.001

30dB

24dB

12dB

0dB

0.0001

20

100

1k

Frequency (Hz)

Figure 5.

10k 20k

20

100

1k

Frequency (Hz)

Figure 6.

10k 20k

6

Product Folder Link(s): PGA2505

PGA2505

www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VA+ = +5V, VA– = –5V, VD– = –5V, and V_COMIN = 0V, unless otherwise noted.

THD + N vs FREQUENCY

(Z_S= 40Ω, R_L= 600Ω, V_COMIN = +2.5V, BW = 22Hz to 22kHz)

0.1

V_OUT= 1.0V_RMSDifferential for All Gain Settings

THD + N vs OUTPUT SWING

(Z_S= 40Ω, R_L= 600Ω, V_COMIN = 0V, BW = 22Hz to 22kHz)

0.1

60dB

0.01

48dB

36dB

30dB

0.001

0dB

24dB

12dB

Gain = 30dB

f = 1kHz

0.0001

0.03

0.3

3

6

20

100

1k

Frequency (Hz)

Figure 7.

10k 20k

Output Amplitude (V_RMS

)

Figure 8.

7

Product Folder Link(s): PGA2505

PGA2505

SBOS396B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com

APPLICATION INFORMATION

space

OVERVIEW

The differential analog output of the PGA2505 is

constantly monitored by a dc servo amplifier loop.

The purpose of the servo loop is to minimize the dc

offset voltage present at the analog outputs by

feeding back an error signal to the input stage of the

programmable gain amplifier. The error signal is then

used to correct the offset. The DC servo may be

disabled by setting the dc bit in the serial control word

to '1'.

The PGA2505 is a digitally-controlled microphone

preamplifier integrated circuit designed to amplify the

output of dynamic and condenser microphones and

drive high-performance audio analog-to-digital

converters (ADCs). A functional block diagram of the

PGA2505 is shown in Figure 9.

The analog input to the preamplifier is provided

differentially at the V_IN+ and V_IN– inputs (pins 24 and

23, respectively). The programmable gain amplifier

can be programmed to either pass through the signal

at unity gain, or apply 9dB to 60dB of gain to the

input signal. The gain of the amplifier is adjustable

over the full 9dB to 60dB range in 3dB steps. The

differential output of the PGA2505 is made available

at V_OUT+ and V_OUT– (pins 15 and 14, respectively).

Gain is controlled using a serial port interface.

Two external capacitors are required for the dc servo

function, with one capacitor connected between C_S11

and C_S12(pins 21 and 20), and the second capacitor

connected between C_S21and C_S22(pins 19 and 18).

A capacitor value of 1µF is recommended for use in

most microphone preamplifier applications. Capacitor

values up to 4.7µF may be used. However, larger

valued capacitors result in longer settling times for

the dc servo loop. Smaller capacitors under 0.22µF

may result in additional distortion in the low frequency

audio bandwidth.

The four-wire serial port interface is used to program

the PGA2505 gain and support functions. A 16-bit

control word is utilized to program these functions

(see Figure 10). A serial data output pin provides

support for daisy-chaining multiple PGA2505 devices

on a single serial interface bus (see Figure 11).

GPO1

GPO2

CS

SCLK

SERIAL

PORT and

GPO3

GPO4

SDI

SDO

OVR

LOGIC

CONTROL

V_COMIN

V_OUT+

V_IN+

PGA

V_OUT

-

V_IN

-

(1)

Gain Range

(2)

C_S1

AGND

DGND

VA+

DC

VA-

VD-

Servo

C_S2

(1) Gain Range: 0dB, or +9dB to +60dB (3dB/step).

(2) C_S1and C_S2are external dc servo integrator capacitors, and are connected across the C_S11/C_S12and C_S21/C_S22pins,

respectively.

Figure 9. PGA2505 Functional Block Diagram

8

Product Folder Link(s): PGA2505

PGA2505

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The PGA2505 includes

a

common-mode servo

An over-range indicator output, OVR, is provided at

pin 6. The OVR pin is an active high,

CMOS-logic-level output. The over-range output is

forced high when the preamplifier output voltage

exceeds one of two preset thresholds. The threshold

is programmed through the serial port interface using

the OR bit. If OR = '0', then the output threshold is set

to 5.1V_RMSdifferential, which is approximately 1dB

below the specified output voltage range. If OR = '1',

then the output threshold is set to 4.0V_RMS

differential, which is approximately 3dB below the

specified output voltage range.

function. This function is enabled and disabled using

the CM bit in the serial control word; see Figure 10.

When enabled, the servo provides common-mode

negative feedback at the input differential pair,

resulting in very low common-mode input impedance.

The differential input impedance is not affected by

this feedback. This function is useful when the source

is floating, or has a high common-mode output

impedance.

When the source is floating, the only connection

between the source and the ground is through the

PGA2505 preamplifier input resistance. The input

common-mode parasitic current is determined by high

output impedance of the source, not by input

impedance of the amplifier. Therefore, input

common-mode interference can be reduced by

lowering the common-mode input impedance while at

the same time not increasing the input common-mode

current. Increasing common-mode current degrades

common-mode rejection. Using the common-mode

servo, overall common-mode rejection can be

improved by suppressing low and medium frequency

common-mode interference.

The PGA2505 includes four programmable digital

outputs, named GPO1, GPO2, GPO3, and GPO4

(pins 2, 3, 4, and 5 respectively), that are controlled

via the serial port interface. These pins are

CMOS-logic-level outputs. These pins may be used

to control relay drivers or switches used for external

preamplifier functions, including input pads, filtering,

polarity reversal, or phantom power.

ANALOG INPUTS AND OUTPUTS

An analog signal is input differentially across the V_IN+

(pin 24) and V_IN– (pin 23) inputs. The input voltage

range and input impedance are provided in the

Electrical Characteristics table. The Applications

Information section of this data sheet provides

additional details regarding typical input circuit

considerations when interfacing the PGA2505 to a

microphone input.

The common-mode servo function is designed to

operate with a total common-mode input capacitance

(including the microphone cable capacitance) of up to

10nF. Beyond this limit, stable servo operation is not

assured.

The common-mode voltage control input, named

V_COMIN (pin 22), allows the PGA2505 output and

input to be dc-biased to a common-mode voltage

between 0V and +2.5V and should not be left floating.

This configuration allows for a dc-coupled interface

between the PGA2505 preamplifier output and the

inputs of common single-supply audio ADCs.

Both V_IN+ and V_IN– are biased at approximately

0.65V below the common-mode input voltage,

supplied at V_COMIN (pin 22). The use of ac-coupling

capacitors (see Figure 10) is highly recommended for

the analog inputs of the PGA2505. If dc-coupling is

required for a given application, the user must take

this offset into account.

The zero crossing control input is provided for

enabling and disabling the internal zero crossing

detector function. This function is enabled and

disabled using the ZC bit in the serial control word;

see Figure 10. Zero crossing detection is used to

force gain changes on zero crossings of the analog

input signal. This configuration limits the glitch energy

associated with switching gain, thereby minimizing

audible artifacts at the preamplifier output. Because

zero crossing detection can add some delay when

performing gain changes (up to 16ms maximum for a

detector timeout event), there may be cases where

the user may wish to disable the function. Setting the

ZC bit high enables zero crossing detection, with gain

changes occurring immediately when programmed.

It is recommended that

a small capacitor be

connected from each analog input pin to analog

ground. Values of at least 50pF are recommended.

See Figure 10 for larger capacitors used for EMI

filtering, which satisfies this requirement.

The analog output is presented differentially across

V_OUT+ (pin 15) and V_OUT– (pin 14). The output

voltage range is provided in the Electrical

Characteristics table. The analog output is designed

to drive a 600Ω differential load while meeting the

published THD+N specifications and typical

performance graphs.

Note that because the zero crossing detector requires

setup, the user should set the ZC bit as a first

operation. Subsequent changes in gain occur on the

zero crossings provided that the ZC bit setting is

maintained.

9

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PGA2505

SBOS396B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com

SERIAL PORT OPERATION

The SCLK input is used to clock serial data into the

SDI pin and out of the SDO pin. The SDI pin

functions as the serial data input, and is used to write

the serial port register. The SDO pin is the shift

register serial output, and is used for either register

read-back or for daisy-chaining multiple PGA2505

devices. Data on SDI are sampled on the rising edge

of SCLK, while data are clocked out of SDO on the

falling edge of SCLK.

The serial port interface for the PGA2505 is

comprised of four wires: CS (pin 9), SCLK (pin 10),

SDI (pin 8), and SDO (pin 11). Figure 10 illustrates

the serial port protocol.

The CS input functions as the chip select and word

latch clock for the serial port. The CS input must be

low in order to clock data into and out of the serial

port. The control word is latched on a low-to-high

transition of the CS input.

The serial port ignores the SCLK and SDI inputs

when CS is high, and the SDO output is set to a high

impedance state while CS is high.

CS

SCLK

SDI

Data Ignored

DC

CM

ZC

OR

D4

D3

D2

D1

0

G5

G4

G3

G2

G1

G0

Data Ignored

High Impedance

SDO

DC Servo Enable

Preamplifier Gain

(Active Low)

where N = G[5:0]^DEC

CM Servo Enable

(Active High)

For N = 0

Gain = 0dB

Zero Crossing Detect

(Active High)

For N = 1 to 17

Gain (dB) = 6 + 3N

Over-Range Indicator Bit

(0 = 5.1V

, 1 = 4.0V )

RMS

For N = 18 to 31

Gain = 60dB

Data for GPO4

Data for GPO3

Data for GPO2

Data for GPO1

Figure 10. Serial Port Protocol

10

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PGA2505

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DAISY-CHAINING MULTIPLE PGA2505

PREAMPLIFIERS

Because the serial port interface may be viewed as a

serial in, serial out shift register, multiple PGA2505

preamplifiers may be connected in a cascaded or

daisy-chained fashion, as shown in Figure 11. The

daisy-chained PGA2505 devices behave as a 16 x

N-bit shift register, where N is the number of

cascaded PGA2505 devices.

To program all of the devices, simply force CS low for

16 x N serial clock periods and clock in 16 x N bits of

control data. The CS input is then forced high to latch

in the new settings.

A timing diagram for the daisy-chain application is

shown in Figure 12.

V_OUT

+

SDI

CS

DOUT

V_OUT

-

CS

Microprocessor

PGA2505

#1

or DSP

SCLK

SDO

DATACLK

V_IN

+

DIN

V_IN

-

V_OUT

+

SDI

CS

V_OUT

-

PGA2505

#2

SCLK

SDO

V_IN

+

V_IN

-

V_OUT

+

SDI

CS

V_OUT

-

PGA2505

#N

SCLK

SDO

V_IN

+

V_IN

-

Figure 11. Daisy-Chain Configuration for Multiple PGA2505 Preamplifiers

CS

SCLK

SDI

G0

DC

G0

DC

G0

DC

Device #N

Device #2

Device #1

Figure 12. Serial Port Operation for Daisy-Chain Operation

11

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PGA2505

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APPLICATION INFORMATION

with analog and digital pins separated basically down

the center of the package. (Note that AGND is on the

opposite side.) However, there must be a low

impedance connection between the analog and digital

grounds at a common return point.

This section provides practical information for

designing the PGA2505 into end applications.

BASIC CIRCUIT CONFIGURATION

The dc common-mode input, V_COMIN (pin 22), can be

connected to analog ground or a dc voltage (such as

the reference or common voltage output of an audio

ADC). When biasing this input to a dc voltage, keep

in mind that both the analog output and input pins will

be level-shifted by the value of the bias voltage.

A typical application configuration, without the input

and output circuitry, is shown in Figure 13.

Power-supply bypass and dc servo capacitors are

shown with recommended values. All capacitors

should be placed as close as possible to the

PGA2505 package to limit inductive noise coupling.

Surface-mount capacitors are recommended (X7R

ceramic for the 0.1µF and 1µF capacitors, and low

ESR tantalum for the 4.7µF capacitors).

The PGA2505 can be placed on a split ground plane,

24

1

V_IN+

AGND

23

2

GPO1

V_IN

-

3

22

21

20

GPO2

V_COMIN

C_S11

4

To Relay Drivers

1mF

GPO3

and Switches

5

GPO4

6

0W

0.1mF

C_S12

OVR

7

19

18

DGND

C_S21

C_S22

0.1mF

17

8

VA-

SDI

9

4.7mF

+

To/From

CS

MPU, MCU,

PGA2505

10

DSP, or Logic

SCLK

SDO

11

VA-

0.1mF

16

VA+

4.7mF

+

0.1mF

12

13

VD-

VA-

VA+

4.7mF

+

0.1mF

15

14

V_OUT

+

4.7mF

+

V_OUT

-

10W

VA-

Figure 13. Basic Circuit Configuration for the PGA2505

12

Product Folder Link(s): PGA2505

PGA2505

www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009

INPUT CIRCUIT CONSIDERATIONS

The blocking capacitors, along with the PGA2505

input resistance, form a high-pass filter circuit. With

the typical input resistance of the PGA2505 specified

in the Electrical Characteristics table, the value of the

capacitor can be chosen to meet the desired low

frequency response for the end application. At the

same time, the value should be no greater than

required, because larger capacitors store more

charge and increase the surge current seen at the

preamplifier when a short circuit occurs on the

microphone input connector.

For proper operation, the input circuit for the

PGA2505 must include several items that are

common to most microphone preamplifiers. Figure 14

shows a typical input circuit configuration. Other

functions, such as input attenuation (pads), filters,

and polarity reversal switches are commonly found in

preamplifier circuits, but are not shown here in order

to focus on the basic input circuit requirements.

The microphone input is typically taken from a

balanced XLR or TRS input connection (XLR shown).

Three 1000pF capacitors provide simple EMI filtering

for the circuit. Additional filtering for low- or

high-frequency noise may be added, depending on

the end application environment. A bridging resistor is

shown and may be selected to provide the desired

To protect the PGA2505 from large surge currents,

power Schottky diodes are placed on the input pins to

both the VA+ and VA– power supplies. Schottky

diodes are used because of the lower turn-on voltage

compared to standard rectifier diodes. Power devices

are required because the surge currents from a large

valued blocking capacitor (47µF) can exceed 4.5A for

a very short duration of time. It is recommended that

the Schottky diode chosen for this application be

specified for at least a 10A surge current.

overall input impedance required for

a

given

microphone. This resistance is in parallel with the

phantom power bias resistors and the PGA2505 input

resistance to set the actual impedance seen by the

microphone.

The use of a series current-limiting resistor before the

protection diodes aids in handling surge currents,

although the resistor adds noise to the circuit. Select

a current-liming resistor value that is as high as

tolerable for the desired noise performance of the

preamplifier circuit.

Connections for +48V phantom power, required for

condenser microphones, are shown in Figure 14. The

phantom power requires an On/Off switch, because

dynamic microphones do not require phantom power

and may be damaged if power is applied.

DC-blocking capacitors are required between the

phantom power connections and the PGA2505

inputs. The blocking capacitors are selected to have

a high working voltage rating, with 50V being the

minimum and 63V recommended for long-term

reliability.

10mF - 47mF

63WV

+

(3)

V_IN+

(2)

(4)

6.81kW

1000pF

Mic Input

VA-

0.25W

VA+

2

1

(1)

3

6.81kW

1000pF

10mF - 47mF

0.25W

(4)

63WV

+

(3)

V_IN-

(2)

Phantom

Power

Switch

+48V

(1) Bridging resistor; used to set the impedance seen by the microphone.

(2) The blocking capacitor value is selected based upon the desired low frequency response.

(3) Current-limiting resistor. Select the highest value tolerable based upon input noise requirements.

(4) Schottky diode; selected for fast turn-on and rated for a minimum of a 10A surge current. Recommended device is the

MBRA120LT3 from ON Semiconductor.

Figure 14. Typical Input Circuit for the PGA2505

13

Product Folder Link(s): PGA2505

PGA2505

SBOS396B–MARCH 2009–REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com

OPERATION WITH V_COMIN = +2.5V

As a suggested alternative, the PGA2505 analog

outputs may be ac-coupled to the ADC inputs,

allowing the PGA2505 to operate with V_COMIN = 0V in

order to achieve best performance. The ac-coupling

capacitors affect the overall low-frequency response

of the preamplifier and converter combination, and

the user is advised to choose a value that best suits

the application requirements.

When interfacing the analog outputs of the PGA2505

with audio ADC inputs, the converter may frequently

have a common-mode dc output pin. This pin may be

connected to the V_COMIN pin of the PGA2505 in order

to facilitate a dc-coupled interface between the two

devices. The common-mode dc voltage level is

typically +2.5V, although some converters may have

a slightly lower value, usually between +2.1V and

+2.5V. There are several issues that must be

considered when operating the PGA2505 in this

fashion.

Figure 15 illustrates a typical PGA2505 to audio ADC

interface using ac-coupling. In addition to the coupling

capacitors, a passive RC filter is required as an

antialiasing filter for the converter. The vast majority

of audio ADCs are of the oversampling delta-sigma

variety, with a simple single-pole filter meeting the

anti-aliasing requirements for this type of converter.

Providing at least 6dB of attenuation also allows the

PGA2505 to operate near full signal swing without

overdriving the ADC inputs.

Both the analog input and output pins of the

PGA2505 are level-shifted by the V_COMIN voltage.

The analog outputs are shifted to the V_COMIN level,

while the analog inputs are shifted to approximately

V_COMIN – 0.65V, as a result of the offset that normally

exists on the input pins. The level-shifting limits the

input and output swing of the PGA2505, reducing the

overall signal-to-noise ratio and degrading the

THD+N performance.

Figure 16 illustrates an application where the V_COMIN

pin of the PGA2505 is connected to the

common-mode dc output of the audio ADC, with a

dc-coupled interface between the PGA2505 analog

outputs and the ADC analog inputs.

Given V_COMIN = +2.5V and gains of 0dB through

60dB, the output swing is limited to less than one-half

that specified in the Electrical Characteristics table.

The output hard-clips at approximately a diode drop

below the VA+ supply rail and a diode drop above

analog ground.

To ensure optimal performance, an output buffer to

the PGA2505 is recommended. Figure 17 illustrates

the use of an OPA1632 as the buffer. Additionally,

the feedback circuitry functions as the antialiasing

filter shown in Figure 15 and Figure 16. Having a

differential buffer with attenuation of 6dB or greater

also allows for the PGA2505 to maximize the output

signal swing, while ensuring that the input swing does

not exceed the full-scale input range of the ADC. An

OPA227 is used to drive the output common-mode of

the OPA1632.

Given V_COMIN = +2.5V and a gain of 0dB, the

practical maximum input or output voltage swing is

approximately 1.0V_RMSdifferential. Increasing the

signal level much beyond this point results in a

substantial increase in distortion.

Plots of THD+N vs Frequency are shown in the

Typical Characteristics section of this data sheet for

both V_COMIN = 0V and +2.5V. The performance

difference can be seen when comparing the plots.

The user must consider whether the difference is

acceptable for the end application.

Coupling

PGA2505

A/D Converter⁽¹⁾

Capacitors

C_C1

R

V_OUT

+

Serial Data Output

2R

C

ADC

PGA

PCM or DSD

+

V_OUT

-

R

C_C2

V_COMIN

Attenuation and

Antialiasing Filter

(1) Recommended devices are the PCM1804, PCM4202, PCM4204, PCM4220, or PCM4222.

Figure 15. PGA2505 Analog Output to ADC Analog Input Interface, AC-Coupled

14

Product Folder Link(s): PGA2505

PGA2505

www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009

PGA2505

A/D Converter⁽¹⁾

R

V_OUT

Serial Data Output

PCM or DSD

C

ADC

PGA

V_OUT

-

V_COMIN

V_COMOutput

Antialiasing Filter

0.1mF

(1) Recommended devices are the PCM1804, PCM4202, PCM4204, PCM4220, or PCM4222.

Figure 16. PGA2505 Analog Output to ADC Analog Input Interface, DC-Coupled

+5V

470W

1nF

3

16

1kW

7

40.2W

15

8

1

24

23

5

V_IN+

A/D Converter⁽¹⁾

+

2.7nF

OPA1632

PGA2505

-

V_IN-

V_COM

4

2

14

22

1nF

6

17

470W

2

3

-5V

6

OPA227

1kW

0.1mF

(1) Recommended devices are the PCM1804, PCM4202, PCM4204, PCM4220, or PCM4222.

Figure 17. PGA2505 Using OPA1632 as an Output Buffer

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May, 2009) to Revision B ..................................................................................................... Page

•

Changed logo on document .................................................................................................................................................. 1

15

Product Folder Link(s): PGA2505

PACKAGE OPTION ADDENDUM

www.ti.com

9-Jun-2009

PACKAGING INFORMATION

Orderable Device

PGA2505IDB

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

DB

24

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PGA2505IDBR

SSOP

DB

24

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jun-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

PGA2505IDBR

SSOP

DB

24

2000

330.0

16.4

8.2

8.8

2.5

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jun-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DB 24

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

PGA2505IDBR

2000

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

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Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

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www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

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interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	PGA2505IDBR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SSOP
包装说明：	SSOP, SSOP24,.3
针数：	24
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	6 weeks
风险等级：	0.97
商用集成电路类型：	AUDIO PREAMPLIFIER
增益：	25.5 dB
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	8.2 mm
湿度敏感等级：	2
信道数量：	1
功能数量：	1
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP24,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	+-5 V
认证状态：	Not Qualified
座面最大高度：	2 mm
子类别：	Audio/Video Amplifiers
最大压摆率：	40 mA
最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.3 mm
Base Number Matches：	1

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