PGA2505
www.ti.com ......................................................................................................................................................... SBOS396B–MARCH 2009–REVISED JUNE 2009
The PGA2505 includes
a
common-mode servo
An over-range indicator output, OVR, is provided at
pin 6. The OVR pin is an active high,
CMOS-logic-level output. The over-range output is
forced high when the preamplifier output voltage
exceeds one of two preset thresholds. The threshold
is programmed through the serial port interface using
the OR bit. If OR = '0', then the output threshold is set
to 5.1VRMS differential, which is approximately 1dB
below the specified output voltage range. If OR = '1',
then the output threshold is set to 4.0VRMS
differential, which is approximately 3dB below the
specified output voltage range.
function. This function is enabled and disabled using
the CM bit in the serial control word; see Figure 10.
When enabled, the servo provides common-mode
negative feedback at the input differential pair,
resulting in very low common-mode input impedance.
The differential input impedance is not affected by
this feedback. This function is useful when the source
is floating, or has a high common-mode output
impedance.
When the source is floating, the only connection
between the source and the ground is through the
PGA2505 preamplifier input resistance. The input
common-mode parasitic current is determined by high
output impedance of the source, not by input
impedance of the amplifier. Therefore, input
common-mode interference can be reduced by
lowering the common-mode input impedance while at
the same time not increasing the input common-mode
current. Increasing common-mode current degrades
common-mode rejection. Using the common-mode
servo, overall common-mode rejection can be
improved by suppressing low and medium frequency
common-mode interference.
The PGA2505 includes four programmable digital
outputs, named GPO1, GPO2, GPO3, and GPO4
(pins 2, 3, 4, and 5 respectively), that are controlled
via the serial port interface. These pins are
CMOS-logic-level outputs. These pins may be used
to control relay drivers or switches used for external
preamplifier functions, including input pads, filtering,
polarity reversal, or phantom power.
ANALOG INPUTS AND OUTPUTS
An analog signal is input differentially across the VIN+
(pin 24) and VIN– (pin 23) inputs. The input voltage
range and input impedance are provided in the
Electrical Characteristics table. The Applications
Information section of this data sheet provides
additional details regarding typical input circuit
considerations when interfacing the PGA2505 to a
microphone input.
The common-mode servo function is designed to
operate with a total common-mode input capacitance
(including the microphone cable capacitance) of up to
10nF. Beyond this limit, stable servo operation is not
assured.
The common-mode voltage control input, named
VCOMIN (pin 22), allows the PGA2505 output and
input to be dc-biased to a common-mode voltage
between 0V and +2.5V and should not be left floating.
This configuration allows for a dc-coupled interface
between the PGA2505 preamplifier output and the
inputs of common single-supply audio ADCs.
Both VIN+ and VIN– are biased at approximately
0.65V below the common-mode input voltage,
supplied at VCOMIN (pin 22). The use of ac-coupling
capacitors (see Figure 10) is highly recommended for
the analog inputs of the PGA2505. If dc-coupling is
required for a given application, the user must take
this offset into account.
The zero crossing control input is provided for
enabling and disabling the internal zero crossing
detector function. This function is enabled and
disabled using the ZC bit in the serial control word;
see Figure 10. Zero crossing detection is used to
force gain changes on zero crossings of the analog
input signal. This configuration limits the glitch energy
associated with switching gain, thereby minimizing
audible artifacts at the preamplifier output. Because
zero crossing detection can add some delay when
performing gain changes (up to 16ms maximum for a
detector timeout event), there may be cases where
the user may wish to disable the function. Setting the
ZC bit high enables zero crossing detection, with gain
changes occurring immediately when programmed.
It is recommended that
a small capacitor be
connected from each analog input pin to analog
ground. Values of at least 50pF are recommended.
See Figure 10 for larger capacitors used for EMI
filtering, which satisfies this requirement.
The analog output is presented differentially across
VOUT+ (pin 15) and VOUT– (pin 14). The output
voltage range is provided in the Electrical
Characteristics table. The analog output is designed
to drive a 600Ω differential load while meeting the
published THD+N specifications and typical
performance graphs.
Note that because the zero crossing detector requires
setup, the user should set the ZC bit as a first
operation. Subsequent changes in gain occur on the
zero crossings provided that the ZC bit setting is
maintained.
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): PGA2505