PS21962-4S原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

PS21962-4S

INTEGRATED POWER FUNCTIONS

600V/5A low-loss 5^thgeneration IGBT inverter bridge for

three phase DC-to-AC power conversion.

Open emitter type.

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

• For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.

• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).

• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply).

• Input interface : 3V, 5V line (High Active).

• UL Approved : Yellow Card No. E80276

APPLICATION

AC100V~200V inverter drive for small power motor control.

Dimensions in mm

Fig. 1 PACKAGE OUTLINES

0.5

38

A

3.5

TERMINAL CODE

B

20×1.778(=35.56 )

0.3

0.05

0.28

35

1.5

1. (VNC)

2. VUFB

3. VVFB

4. VWFB

5. UP

0.2

1.778

16-0.5

1

17

6. VP

7. WP

8. VP1

9. VNC *

10. UN

11. VN

12. WN

13. VN1

14. FO

15. CIN

16. VNC *

17. NC

18. NW

19. NV

20. NU

Type name

QR

0.8

Lot No.

3 MIN

Code

HEAT SINK SIDE

21.

22.

23.

24.

W

V

U

P

18

25

0.28

0.2

8-0.6

0.5

25. NC

2.54

4-C1.2

2.5 MIN

14×2.54(=35.56)

0.5

(2.656)

0.5

(1.2)

(2.756)

HEAT SINK SIDE

DETAIL A

DETAIL B

*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and

leave another one open.

Mar. 2007

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)

INVERTER PART

Symbol

Parameter

Condition

Ratings

Unit

V

Applied between P-NU, NV, NW

Supply voltage

Supply voltage (surge)

450

500

VCC

VCC(surge)

VCES

±IC

V

Collector-emitter voltage

Each IGBT collector current

Each IGBT collector current (peak)

Collector dissipation

V

600

5

A

TC = 25°C

±ICP

PC

Tj

10

A

TC = 25°C, less than 1ms

TC = 25°C, per 1 chip

21.3

–20~+125

W

°C

Junction temperature

(Note 1)

Note 1: The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C). However, to

ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).

CONTROL (PROTECTION) PART

Symbol

VD

Parameter

Control supply voltage

Condition

Ratings

20

Unit

V

Applied between VP1-VNC, VN1-VNC

VDB

Control supply voltage

Applied between VUFB-U, VVFB-V, VWFB-W

V

20

Applied between UP, VP, WP, UN, VN,

WN-VNC

VIN

Input voltage

V

–0.5~VD+0.5

Fault output supply voltage

Applied between FO-VNC

–0.5~VD+0.5

1

–0.5~VD+0.5

VFO

V

mA

V

IFO

VSC

Fault output current

Current sensing input voltage

Sink current at FO terminal

Applied between CIN-VNC

TOTAL SYSTEM

Symbol

Ratings

400

Unit

V

Condition

Parameter

Self protection supply voltage limit

(short circuit protection capability)

VD = 13.5~16.5V, Inverter part

Tj = 125°C, non-repetitive, less than 2µs

VCC(PROT)

Module case operation temperature

(Note 2)

–20~+100

–40~+125

°C

TC

Tstg

Storage temperature

60Hz, Sinusoidal, 1 minute,

Between pins and heat-sink plate

Viso

Isolation voltage

1500

Vrms

Note 2: TC measurement point

Control terminals

DIP-IPM

11.6mm

3mm

IGBT chip position

FWD chip position

T

C

point

Heat sink side

Power terminals

Mar. 2007

2

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

THERMAL RESISTANCE

Limits

Symbol

Parameter

Condition

Unit

Min.

—

Typ.

—

Max.

4.7

Rth(j-c)Q

Rth(j-c)F

Inverter IGBT part (per 1/6 module)

Inverter FWD part (per 1/6 module)

°C/W

Junction to case thermal

resistance (Note 3)

—

5.4

Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM

and heat-sink.

The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal

conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and

the thermal conductivity is 1.0W/m·k.

ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)

INVERTER PART

Limits

Symbol

VCE(sat)

Parameter

Condition

Unit

V

Min.

—

Typ.

Max.

2.20

2.30

2.20

1.60

—

VD = VDB = 15V

VIN = 5V

IC = 5A, Tj = 25°C

IC = 5A, Tj = 125°C

Tj = 25°C, –IC = 5A, VIN = 0V

1.70

1.80

1.70

1.00

0.30

1.40

0.50

—

Collector-emitter saturation

voltage

—

FWD forward voltage

VEC

ton

trr

tc(on)

toff

V

µs

0.50

—

µs

VCC = 300V, VD = VDB = 15V

—

↔

5V

IC = 5A, Tj = 125°C, VIN = 0

0.50

2.00

0.80

1

Switching times

—

Inductive load (upper-lower arm)

tc(off)

—

Tj = 25°C

Tj = 125°C

—

Collector-emitter cut-off

current

ICES

mA

VCE = VCES

—

10

CONTROL (PROTECTION) PART

Symbol

Parameter

Limits

Typ.

—

Condition

Unit

mA

Min.

—

Max.

2.80

0.55

2.80

0.55

—

VD = VDB = 15V

VIN = 5V

Total of VP1-VNC, VN1-VNC

VUFB-U, VVFB-V, VWFB-W

Total of VP1-VNC, VN1-VNC

VUFB-U, VVFB-V, VWFB-W

—

ID

Circuit current

VD = VDB = 15V

VIN = 0V

—

4.9

—

V

VFOH

VFOL

VSC(ref)

IIN

VSC = 0V, FO terminal pull-up to 5V by 10kΩ

VSC = 1V, IFO = 1mA

Tj = 25°C, VD = 15V

VIN = 5V

Fault output voltage

—

0.95

0.53

1.50

12.0

12.5

13.0

—

0.43

0.70

10.0

10.5

10.3

10.8

20

0.48

1.00

—

V

mA

V

Short circuit trip level

Input current

(Note 4)

Trip level

UVDBt

UVDBr

UVDt

UVDr

tFO

Reset level

—

V

Control supply under-voltage

protection

Tj ≤ 125°C

Trip level

—

V

Reset level

—

V

—

2.1

1.3

µs

V

(Note 5)

Fault output pulse width

ON threshold voltage

OFF threshold voltage

—

2.6

Vth(on)

Vth(off)

0.8

—

V

Applied between UP, VP, WP, UN, VN, WN-VNC

ON/OFF threshold hysteresis

voltage

0.35

0.65

—

V

Vth(hys)

Note 4: Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is

less than 1.7 times of the current rating.

5: Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure.

Mar. 2007

3

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

MECHANICAL CHARACTERISTICS AND RATINGS

Parameter

Limits

Typ.

Condition

Unit

N·m

Min.

0.59

Max.

0.78

Mounting screw : M3

—

Mounting torque

Weight

Recommended : 0.69 N·m

(

)

Note 6

—

10

—

g

µm

(

)

Heat-sink flatness

Note 7

–50

100

Note 6: Plain washers (ISO 7089~7094) are recommended.

Note 7: Flatness measurement position

Measurement position

4.6mm

+

–

DIP-IPM

Heat sink side

–

+

Heat sink side

RECOMMENDED OPERATION CONDITIONS

Symbol

Parameter

Supply voltage

Limits

Typ.

Condition

Unit

Min.

Max.

VCC

Applied between P-NU, NV, NW

0

300

15.0

—

400

16.5

18.5

1

V

VD

Control supply voltage

Control supply variation

Applied between VP1-VNC, VN1-VNC

Applied between VUFB-U, VVFB-V, VWFB-W

13.5

13.0

–1

VDB

V

∆VD, ∆VDB

tdead

V/µs

µs

Arm shoot-through blocking time For each input signal, TC ≤ 100°C

1.5

—

fPWM

PWM input frequency

TC ≤ 100°C, Tj ≤ 125°C

VCC = 300V, VD = VDB = 15V,

P.F = 0.8, sinusoidal PWM,

Tj ≤ 125°C, TC ≤ 100°C

—

20

kHz

fPWM = 5kHz

—

2.5

Arms

Allowable r.m.s. current

IO

fPWM = 15kHz

—

1.5

(Note 8)

—

0.5

—

PWIN(on)

PWIN(off)

VNC

Allowable minimum input

pulse width

µs

(Note 9)

VNC variation

–5.0

5.0

Between VNC-

(including surge)

NU, NV, NW

V

Note 8: The allowable r.m.s. current value depends on the actual application conditions.

9: IPM might not make response if the input signal pulse width is less than the recommended minimum value.

Mar. 2007

4

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

Fig. 2 THE DIP-IPM INTERNAL CIRCUIT

DIP-IPM

V

UFB

P

U

HVIC

Di1

IGBT1

V

UB

V

CC

V

P1

U

OUT

U

P

U

P

VUS

COM

V

NC

IGBT2

Di2

V

VB

P

V

VFB

V

P

VOUT

V

VS

V

IGBT3

IGBT4

IGBT5

IGBT6

Di3

Di4

Di5

Di6

V

WB

V

WFB

W

P

W

OUT

W

P

V

WS

W

LVIC

U

V

OUT

V

N1

V

CC

NU

NV

OUT

U

N

U

N

V

N

V

N

W

N

W

OUT

Fo

CIN

NW

V

NO

V

NC

GND

CIN

Mar. 2007

5

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

Fig. 3 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS

[A] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter)

a1. Normal operation : IGBT ON and carrying current.

a2. Short circuit detection (SC trigger).

a3. IGBT gate hard interruption.

a4. IGBT turns OFF.

a5. FO outputs (tFO(min) = 20µs).

a6. Input “L” : IGBT OFF.

a7. Input “H” : IGBT ON.

a8. IGBT OFF in spite of input “H”.

Lower-side control

input

a6 a7

Protection circuit state

Internal IGBT gate

SET

a2

RESET

a3

SC

a4

a1

Output current Ic

a8

SC reference voltage

Sense voltage of the

shunt resistor

CR circuit time

constant DELAY

Error output Fo

a5

[B] Under-Voltage Protection (Lower-side, UVD)

b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.

b2. Normal operation : IGBT ON and carrying current.

b3. Under voltage trip (UVDt).

b4. IGBT OFF in spite of control input condition.

b5. FO outputs (tFO ≥ 20µs and FO outputs continuously during UV period).

b6. Under voltage reset (UVDr).

b7. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state

RESET

b1

SET

RESET

UVDr

Control supply voltage V

D

b6

UVDt

b2

b3

b4

b7

Output current Ic

Error output Fo

b5

Mar. 2007

6

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

[C] Under-Voltage Protection (Upper-side, UVDB)

c1. Control supply voltage rising : After the voltage level reaches UVDBr, the circuits start to operate when next input is applied.

c2. Normal operation : IGBT ON and carrying current.

c3. Under voltage trip (UVDBt).

c4. IGBT OFF in spite of control input signal level, but there is no FO signal outputs.

c5. Under voltage reset (UVDBr).

c6. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state

RESET

c1

SET

RESET

UVDBr

Control supply voltage VDB

c5

UV^DBt

c2

c3

c4

c6

Output current Ic

Error output Fo

High-level (no fault output)

Fig. 4 RECOMMENDED MCU I/O INTERFACE CIRCUIT

5V line

DIP-IPM

10kΩ

UP,VP,WP,UN,VN,WN

MCU

3.3kΩ (min)

Fo

NC(Logic)

V

Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the

wiring impedance of the printed circuit board.

The DIP-IPM input section integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external

filtering resistor, pay attention to the turn-on threshold voltage.

Fig. 5 WIRING CONNECTION OF SHUNT RESISTOR

DIP-IPM

Each wiring inductance should be less than 10nH.

Equivalent to the inductance of a copper

pattern in dimension of width=3mm,

thickness=100µm, length=17mm

VNC

NU

NV

NW

Shunt resistors

Please make the GND wiring connection

of shunt resistor to the VNC terminal

as close as possible.

Mar. 2007

7

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21962-4S

TRANSFER-MOLD TYPE

INSULATED TYPE

Fig. 6 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT

C1: Electrolytic capacitor with good temperature characteristics C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering

C2 C1 C2

C2

C1

Bootstrap negative electrodes

should be connected to U, V,

W terminals directly and

separated from the main output

wires.

V

UFB

V

VFB

V

WFB

DIP-IPM

P

HVIC

V

P1

VUB

VCC

C3

U

P

UP

UOUT

U

VUS

VVB

V

P

VP

VOUT

V

VVS

M

VWB

W

P

WOUT

WP

V

NC

W

COM

VWS

LVIC

UOUT

V

N1

NU

VCC

C3

5V line

VOUT

U

N

UN

NV

V

N

VN

W

N

WN

W

OUT

Fo

F

o

CIN

NW

VNO

V

NC

C

GND

Long wiring here might

cause short-circuit.

CIN

Long wiring here might cause

SC level fluctuation and

malfunction.

Long GND wiring here might

generate noise to input and

cause IGBT malfunction.

15V line

Shunt resistors

A

N1

B

R1

C4

+

-

Vref

B

R1

C4

+

-

R1

C4

OR Logic

+

-

Comparator

External protection circuit

Note 1

:

Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each in-

put should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage.

2

3

4

5

: Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.

: FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ.

: To prevent erroneous protection, the wiring of A, B, C should be as short as possible.

: The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the

wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4.

6

7

8

9

: All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency character-

istic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.)

: To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.

Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.

: Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and

leave another one open.

: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.

10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended

to connect control GND and power GND at only a point.

11 : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V).

12 : OR logic output high level should exceed the maximum short circuit trip level (Vsc(ref): max.0.53V).

Mar. 2007

8

型号:	PS21962-4S
生命周期：	Not Recommended
零件包装代码：	DMA
包装说明：	,
针数：	25
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.22
Is Samacsys：	N
模拟集成电路 - 其他类型：	AC MOTOR CONTROLLER
JESD-30 代码：	R-XDMA-T25
功能数量：	1
端子数量：	25
最大输出电流：	10 A
封装主体材料：	UNSPECIFIED
封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY
认证状态：	Not Qualified
最大供电电压 (Vsup)：	16.5 V
最小供电电压 (Vsup)：	13.5 V
标称供电电压 (Vsup)：	15 V
表面贴装：	NO
技术：	HYBRID
端子形式：	THROUGH-HOLE
端子位置：	DUAL
Base Number Matches：	1

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